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74LX1G132 Datasheet(PDF) 1 Page - STMicroelectronics |
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74LX1G132 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 11 page  1/11 April 2004 s 5V TOLERANT INPUTS s HIGH SPEED: tPD = 5.5ns (MAX.) at VCC =3V s LOW POWER DISSIPATION: ICC =1µA(MAX.) at TA =25°C s TYPICAL HYSTERESIS: Vh=1V at VCC=4.5V s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL = 24mA (MIN) at VCC =3V s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 5.5V (1.2V Data Retention) s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LX1G132 is a low voltage CMOS SINGLE 2-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. This together with its schmitt trigger function allows it to be used on line receivers with slow rise/fall input signals. All inputs and outputs are equipped with protection circuits against static discharge. 74LX1G132 SINGLE 2-INPUT SCHMITT NAND GATE PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE T & R SOT23-5L 74LX1G132STR SOT323-5L 74LX1G132CTR SOT323-5L SOT23-5L |
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