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AT94S10AL Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT94S10AL Datasheet(HTML) 6 Page - ATMEL Corporation |
6 / 31 page 6 AT94S Secure Family 2314D–FPSLI–2/04 Bit Ordering Protocol The most significant bit is the first bit of a byte transmitted on the cSDA line for the Device Address Byte and the EEPROM Address Bytes. It is followed by the lesser sig- nificant bits until the eighth bit, the least significant bit, is transmitted. However, for Data Bytes (both writing and reading), the first bit transmitted is the least significant bit. This protocol is shown in the diagrams below. Device Address Byte The contents of the Device Address Byte are shown below, along with the order in which the bits are clocked into the device. The CE pin cannot be used for device selection in programming mode (i.e., when SER_EN is drive Low). Figure 2. Start and Stop Conditions Where:R/W = 1 Read = 0 Write EEPROM Address The EEPROM Address consists of three bytes on the 1-Mbit part. Each Address Byte is followed by an Acknowledge Bit (provided by the Configurator). These bytes define the normal address space of the Configurator. The order in which each byte is clocked into the Configurator is also indicated. Unused bits in an Address Byte must be set to “0”. Exceptions to this are when reading Device and Manufacturer Codes. 8th Bit STOP Condition Byte n cSCK cSDA START Condition tWR ACK BIT Device Address Byte MSB LSB 10 10 011 R/W 1st 2nd 3rd 4th 5th 6th 7th 8th MSB LSB MSB LSB MSB LSB 0 0 0 0000 A E16 ACK A E15 A E14 A E13 A E12 A E11 A E10 A E9 A E8 ACK A E7 A E6 A E5 A E4 A E3 A E2 A E1 A E0 ACK 1st 2nd 3rd 4th 5th 6th 7th 8th 1st 2nd 3rd 4th 5th 6th 7th 8th 1st 2nd 3rd 4th 5th 6th 7th 8th 512-Kbit/1-Mbit Page Length 1-Mbit Address Space Byte Order 512-Kbit Address Space |
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