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PRELIMINARYINFORMATION

Rev.00B

01/26/04

IS24C52

Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published

information and before placing orders for products.

2k-bit 2-WIRE SERIAL CMOS EEPROM

with Permanent Write-Protection

FEATURES

• Two-Wire Serial Interface

– Bidirectional data transfer protocol

• Organization:

– 256-bit x 8-bit

• Data Protection Features

– Write Protect Pin

– Permanent Software Protection

• 16-Byte Page Write Buffer

– Partial Page-writes permitted

• Low Power CMOS Technology

– Active Current less than 2 mA (5V)

– Standby Current less than 6 µA (5V)

– Standby Current less than 2 µA (2.5V)

• Low Voltage Operation

– IS24C52-2: Vcc = 1.8V to 5.5V

– IS24C52-3: Vcc = 2.5V to 5.5V

ADVANCED INFORMATION

JANUARY 2004

• Random or Sequential Read Modes

• Filtered Inputs for Noise Suppression

• Self timed Write cycle with auto clear

– 5 ms @ 2.5V

• High Reliability

– Endurance: 1,000,000 Cycles

– Data Retention: 40 Years

• Commercial and Industrial temperature ranges

•

8-pin SOIC, 8-pin TSSOP, and 8-pin MSOP

DESCRIPTION

The IS24C52 is an electrically erasable PROM device

that uses the standard 2-wire interface for

communications. The IS24C52 contains a memory array

of 2,048-bits (256K x 8), and is further subdivided into 16

pages of 16 bytes each for page-write mode. The

software write-protection feature is initiated with a unique

irreversible instruction. After this command is

transmitted, the first 128 bytes of the array become

permanently read-only. This feature is popular in

applications like DRAM DIMMs to retain DRAM related

data. This EEPROM is offered in wide operating voltages

3) to be compatible with most application voltages. ISSI

designed the IS24C52 as a low-cost and low-power 2-

wire EEPROM solution. The devices are packaged in 8-

pin SOIC, and 8-pin TSSOP, and 8-pin MSOP.

The IS24C52 maintains compatibility with the popular 2-

wire bus protocol, so it is easy to use in applications

implementing this bus type. The simple bus consists of

the Serial Clock wire (SCL) and the Serial Data wire

(SDA). Using the bus, a Master device such as a

microcontroller is usually connected to one or more

Slave devices such as the IS24C52. The bit stream over

the SDA line includes a series of bytes, which identifies

a particular Slave device, an instruction, an address

within that Slave device, and a series of data, if

appropriate. The IS24C52 has a Write Protect pin (WP)

to allow blocking of any write instruction transmitted over

the bus.