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UPD780023AGC-XXX-AB8 Datasheet(PDF) 8 Page - NEC |
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UPD780023AGC-XXX-AB8 Datasheet(HTML) 8 Page - NEC |
8 / 96 page 8 µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY Data Sheet U14042EJ4V0DS OVERVIEW OF FUNCTIONS (1/2) Part Number µPD780021A µPD780022A µPD780023A µPD780024A Item µPD780021AY µPD780022AY µPD780023AY µPD780024AY Internal ROM 8 KB 16 KB 24 KB 32 KB memory High-speed RAM 512 bytes 1024 bytes Memory space 64 KB General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution On-chip minimum instruction execution time cycle variable function When main system • Expanded-specification products of µPD780021A, 780022A, 780023A, 780024A: clock selected 0.166 µs/0.333 µs/0.666 µs/1.33 µs/2.66 µs (@12 MHz, VDD = 4.5 to 5.5 V operation) • µPD780021AY,780022AY,780023AY,780024AYandconventionalproductsofµPD780021A, 780022A, 780023A, 780024A: 0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@8.38 MHz, VDD = 4.0 to 5.5 V operation) When subsystem 122 µs (@ 32.768 kHz operation) clock selected Instruction set • 16-bit operation • Multiply/divide (8 bits × 8 bits,16 bits ÷ 8 bits) • Bit manipulation (set, reset, test, Boolean operation) • BCD adjust, etc. I/O ports Total: 51 • CMOS input: 8 • CMOS I/O: 39 • N-ch open-drain I/O (5 V withstanding voltage): 4 A/D converter • 8-bit resolution × 8 channels • Low-voltage operation available: AVDD = 1.8 to 5.5 V Serial interface • µPD780021A, 780022A, 780023A, 780024A UART mode: 1 channel 3-wire serial I/O mode: 2 channels • µPD780021AY, 780022AY, 780023AY, 780024AY UART mode: 1 channel 3-wire serial I/O mode: 1 channel I2C bus mode (multimaster supporting): 1 channel Timers • 16-bit timer/event counter: 1 channel • 8-bit timer/event counter: 2 channels • Watch timer: 1 channel • Watchdog timer: 1 channel Timer outputs 3 (8-bit PWM output capable: 2) time |
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