UCC28521, UCC28528

SLUS608B − JANUARY 2005 REVISED JUNE 2005

10

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DETAILED PIN DESCRIPTIONS (CONTINUED)

RT (Pin 2): A resistor between RT and GND programs the oscillator frequency, measured at CT_BUFF. In all

options, the PWM stage operates at the frequency that is measured at CT_BUFF. In the UCC28521 the PFC

stage operates at the same frequency as the PWM stage. The voltage is dc (nominally 3 V); do not connect a

capacitor to this pin in an attempt to stabilize the voltage. Instead, connect the GND side of the

oscillator-programming resistor closer to the GND pin. The recommended range of resistors is 45 k

Ω to 500

k

as measured at CT_BUFF, according to the following equation:

R

1

31

1

f

S

* 2.0

SS2 (pin 13): A capacitor between SS2 and GND programs the softstart duration of the PWM stage gate drive.

When the UVLO2 comparator enables the PWM stage, an internal 10.5-

µA current source charges the external

capacitor at SS2 to 3 V to ramp the voltage at VERR during startup. This allows the GT2 duty cycle to increase

C

t

SS

10.5

3

,

Farads

In the event of a disable command or a UVLO2 dropout, SS2 quickly discharges to ground to disable the PWM

stage gate drive.

VAOUT (Pin 1): This transconductance voltage amplifier output regulates the PFC stage output voltage and

operates between GND and 5.5 V maximum to prevent overshoot. Connect the voltage compensation

components between VAOUT and GND. When this output goes below 1 V, the multiplier output current goes

to zero. When this output falls below 0.33 V, the zero power detect comparator ensures the PFC stage gate drive

is turned off. In the linear range, this pin sources or sinks up to 30

µA. A slew rate enhancement feature enables

VAOUT to sink or source up to 3.3 mA, when operating outside the linear range.

VCC (Pin 9): Chip positive supply voltage that should be connected to a stable source of at least 20 mA between

12 V and 17 V for normal operation. Bypass VCC directly to GND with a 0.1

µF or larger ceramic capacitor to

absorb supply current spikes caused by the fast charging of the external MOSFET gate capacitances.

VERR (Pin 7): The voltage at this pin controls the GT2 duty cycle and is connected to the feedback error signal

from an external amplifier in the PWM stage. This pin is clamped to a maximum of 3 V and can demand 100%

duty cycle at GT2. The typical pull-up current flowing out of this pin is 10

µA.

VFF (Pin 19): The output current from this pin comes from an internal current mirror that divides the IAC input

current by 2. The input voltage feedforward signal for the multiplier is then generated across an external

single-pole R/C filter connected between VFF and GND. At low line, the VFF voltage should be set to 1.4 V.

VREF (Pin 20): This is the output of an accurate 7.5-V reference that powers most of the internal circuitry and

can deliver over 10 mA, with a typical load regulation of 5 mV ensured for an external load of up to 6 mA. The

internal reference is current limited to 25 mA, which protects the part if VREF is short-circuited to ground. VREF

should be bypassed directly to GND with a ceramic capacitor between 0.1

µF and 10 µF for stability. VREF is

disabled and remains at 0 V when VCC is below the 9.7-V UVLO threshold.

VSENSE (Pin 3): Inverting input to the PFC transconductance voltage amplifier, which serves as the PFC

feedback connection point. When VSENSE operates within +/− 0.35 V of its steady-state value, the current at

this range, the magnitude of the current of VAOUT is increased in order to enhance the slew rate for rapid voltage

control recovery in the PFC stage. Decisive activation and deactivation of the voltage control recovery is

internally implemented with about 120 mV of hysteresis at VSENSE. VSENSE is internally connected to the PFC

OVP, Enable and UVLO2 comparators as well.