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LT4250H Datasheet(PDF) 5 Page - Linear Technology |
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LT4250H Datasheet(HTML) 5 Page - Linear Technology |
5 / 12 page 5 LT4250L/LT4250H 4250lhf PIN FUNCTIONS OV (Pin 2): Analog Overvoltage Input. When OV is pulled above the 1.255V threshold, an overvoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until OV drops below the 1.235V threshold. UV (Pin 3): Analog Undervoltage Input. When UV is pulled below the 1.125V threshold, an undervoltage condition is detected and the GATE pin will be immedi- ately pulled low. The GATE pin will remain low until UV rises above the 1.255 threshold. The UV pin is also used to reset the electronic circuit breaker. If the UV pin is cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and a normal power-up sequence will occur. The response time for this pin is 1.5 µs. Add an external capacitor to this pin for additional filtering. VEE (Pin 4): Negative Supply Voltage Input. Connect to the lower potential of the power supply. SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense resistor placed in the supply path between VEE and SENSE, the overcurrent condition will pull down the GATE pin and regulate the voltage across the resistor to be 50mV. If the overcurrent condition exists for more than 500 µs the electronic circuit breaker will trip and turn off the external MOSFET. If the current limit value is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the current limit feature, VEE and SENSE can be shorted together. GATE (Pin 6): Gate Drive Output for the External N-Channel MOSFET. The GATE pin will go high when the following start-up conditions are met: the UV pin is high, the OV pin is low, (VSENSE – VEE) < 50mV and the VDD pin is greater than VUVLOH. The GATE pin is pulled high by a 45 µA current source and pulled low with a 50mA current source. During current limit the GATE pin is pulled low using a 100mA current source. DRAIN (Pin 7): Analog Drain Sense Input. Connect this pin to the drain of the external N-channel MOSFET and the V – pin of the power module. When the DRAIN pin is below VDL, the PWRGD/PWRGD pin will latch to indicate the switch is on. VDD (Pin 8): Positive Supply Voltage Input. Connect this pin to the higher potential of the power supply inputs and the V + pin of the power module. An undervoltage lockout circuit disables the chip until the VDD pin is greater than the 16V VUVLOH threshold. BLOCK DIAGRA – + + – + – DRAIN 4250 BD GATE SENSE VEE VEE VDL OUTPUT DRIVE PWRGD/PWRGD 50mV VCC VDD REF REF UV OV LOGIC VCC AND REFERENCE GENERATOR – + + – ∆VGATE VGH 500 µs DELAY GATE DRIVER UVLO |
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