V385

V385 Datasheet

1

3/30/05

Revision 1.6

Integrated Circuit Systems • 525 Race St reet, San Jose, CA 95 126 • tel (408) 297-1201 • w w w. icst.com

General Description

The V385 transmitter converts 28 bits of 3.3 V

CMOS/TTL into 4 Low Voltage Differential Signaling

(LVDS) data streams while the transmit clock input is

transmitted in parallel with the data streams over a fifth

LVDS link. The V385 can be programmed for rising

edge or falling edge clocks through pin R_FB.

ICS manufactures a large variety of video application

devices. Consult ICS for all of your video application

requirements.

Pin Assignment

Features

DS90C385, TI SN65LVDS93 and THine

THC63LVDM83

streams

bandwidth

Block Diagram

12

1

11

2

10

VCC

3

9

TxIN5

4

5

6

7

8

16

15

14

13

56-pin TSSOP

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

TxIN6

TxIN7

TxIN8

TxIN9

TxIN10

GND

VCC

TxIN11

TxIN12

TxIN13

GND

TxIN14

TxIN15

TxIN16

R_FB

TxIN17

TxIN18

TxIN19

GND

TxIN20

TxIN21

TxIN22

TxIN23

TxIN24

TxIN25

VCC

GND

TxIN26

PWRDWN

PLL_GND

PLL_GND

PLL_VCC

LVDS_GND

LVDS_GND

LVDS_GND

LVDS_VCC

TxOUT3+

TxOUT3-

TxCLKOUT+

TxCLKOUT-

TxOUT2+

TxOUT2-

TxCLKIN

TxOUT1+

TxOUT1-

TxOUT0+

TxOUT0-

TxIN27

TxIN0

TxIN1

GND

TxIN2

TxIN3

TxIN4

TTL to

LVDS

TxOUT0+

PLL

TxOUT0-

TxOUT1+

TxOUT1-

TxOUT2+

TxOUT2-

TxOUT3+

TxOUT3-

TxCLKOUT+

TxCLKOUT-

24

Red, Green, Blue

CLOCK

PWRDWN

R_FB

CONTROL

DATA ENABLE

VSYNC

HSYNC