256M GDDR SDRAM

K4D553238F-GC

- 7 -

Rev 1.3 (Mar. 2005)

• Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)

- Apply VDD before VDDQ .

- Apply VDDQ before VREF & VTT

2. Start clock and maintain stable condition for minimum 200us.

3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .

4. Issue precharge command for all banks of the device.

5. Issue a EMRS command to enable DLL

(Minimum 20 clock cycles are recommended prior to MRS command, however not mandatory just in case tMRD met)

*1

6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

8. Issue at least 2 or more auto-refresh commands.

9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6&7 is regardless of the order

FUNCTIONAL DESCRIPTION

Power up & Initialization Sequence

Command

tRP

tMRD

precharge

ALL Banks

2nd Auto

Refresh

Mode

Register Set

Any

Command

1st Auto

Refresh

EMRS

MRS

tMRD.

DLL Reset

precharge

ALL Banks

Inputs must be

stable for 200us

200 Clock min.

tMRD

CK,CK

* When the operating frequency is changed, DLL reset should be required again.

After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.