64Kx36/x32 Synchronous SRAM

- 3 -

Rev 2.0

Nov 2003

K7A203200B

K7A203600B

64Kx36 & 64Kx32-Bit Synchronous Pipelined Burst SRAM

The K7A203600B and K7A203200B are 2,359,296-bit Syn-

chronous Static Random Access Memory designed for high

performance second level cache of Pentium and Power PC

based System.

It is organized as 64K words of 36/32 bits and integrates

address and control registers, a 2-bit burst address counter

and added some new functions for high performance cache

RAM applications; GW, BW, LBO, ZZ. Write cycles are inter-

nally self-timed and synchronous.

Full bus-width write is done by GW, and each byte write is

performed by the combination of WEx and BW when GW is

Burst cycle can be initiated with either the address status

processor(ADSP) or address status cache controller(ADSC)

inputs. Subsequent burst addresses are generated inter-

nally in the system

′s burst sequence and are controlled by

the burst address advance(ADV) input.

LBO pin is DC operated and determines burst sequence(lin-

ear or interleaved).

ZZ pin controls Power Down State and reduces Stand-by

current regardless of CLK.

The K7A203600B and K7A203200B are fabricated using

SAMSUNG

′s high performance CMOS technology and is

available in a 100pin TQFP package. Multiple power and

ground pins are utilized to minimize ground bounce.

GENERAL DESCRIPTION

FEATURES

LOGIC BLOCK DIAGRAM

• Synchronous Operation.

• 2 Stage Pipelined operation with 4 Burst.

• On-Chip Address Counter.

• Self-Timed Write Cycle.

• On-Chip Address and Control Registers.

or 2.5V+0.4V/-0.125V for 2.5V I/O.

• 5V Tolerant Inputs Except I/O Pins.

• Byte Writable Function.

• Global Write Enable Controls a full bus-width write.

• Power Down State via ZZ Signal.

• LBO Pin allows a choice of either a interleaved burst or a linear

burst.

• Three Chip Enables for simple depth expansion with No Data Cont-

nention ; 2cycle Enable, 1cycle Disable.

• Asynchronous Output Enable Control.

• ADSP, ADSC, ADV Burst Control Pins.

• TTL-Level Three-State Output.

• 100-TQFP-1420A .

• Operating in commeical and industrial temperature range.

CLK

LBO

ADV

ADSC

ADSP

CS1

CS2

CS2

GW

BW

WEx

OE

ZZ

DQa0 ~ DQd7

BURST CONTROL

LOGIC

BURST

64Kx36/32

ADDRESS

CONTROL

OUTPUT

DATA-IN

ADDRESS

COUNTER

MEMORY

ARRAY

REGISTER

REGISTER

BUFFER

LOGIC

A

′0~A′1

A0~A1

A0~A15

REGISTER

DQPa ~ DQPd

A2~A15

(x=a,b,c,d)

36/32 or 18

FAST ACCESS TIMES

PARAMETER

Symbol

-14

Unit

Cycle Time

tCYC

7.2

ns

Clock Access Time

tCD

4.0

ns

Output Enable Access Time

tOE

4.0

ns