1

K9F1G08U0A

K9F1G08R0A

K9K2G08U1A

FLASH MEMORY

Document Title

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near your office.

Revision No

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Remark

Advance

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

History

1. Initial issue

1. The tADL(Address to Data Loading Time) is added.

- tADL Minimum 100ns (Page 11, 23~26)

- tADL is the time from the WE rising edge of final address cycle

to the WE rising edge of first data cycle at program operation.

2. Added Addressing method for program operation

1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.

1. PKG(TSOP1, WSOP1) Dimension Change

1. Technical note is changed

2. Notes of AC timing characteristics are added

3. The description of Copy-back program is changed

4. Voltage range is changed

-1.7V~1.95V -> 1.65V~1.95V

5. Note2 of Command Sets is added

1. CE access time : 23ns->35ns (p.11)

1. The value of tREA for 3.3V device is changed.(18ns->20ns)

2. EDO mode is added.

1. The flow chart to creat the initial invalid block table is cahnged.

Draft Date

Aug. 24. 2003

Jan. 27. 2004

Apr. 23. 2004

May. 19. 2004

Jan. 21. 2005

Feb. 14. 2005

May. 24. 2005

May 6. 2005