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A29DL163TV-70 Datasheet(PDF) 8 Page - AMIC Technology |
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A29DL163TV-70 Datasheet(HTML) 8 Page - AMIC Technology |
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8 / 47 page  A29DL16x Series PRELIMINARY (September, 2004, Version 0.0) 7 AMIC Technology, Corp. sleep mode is independent of the CE , WE and OE control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET : Hardware Reset Pin The RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET pulse. When RESET is held at VSS ± 0.3V, the device draws CMOS standby current (ICC4 ). If RESET is held at VIL but not within VSS ± 0.3V, the standby current will be greater. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase operation, the RY/ BY pin remains a “0” (busy) until the internal reset operation is complete, which requires a time tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is not executing (RY/ BY pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin return to VIH. Refer to the AC Characteristics tables for RESET parameters and diagram. Output Disable Mode When the OE input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. A29DL16x Device Bank Divisions Bank 1 Bank 2 Device Part Number Megabits Sector Sizes Megabits Sector Sizes A29DL162 2 Mbit Eight 8 Kbyte/4 Kword, three 64 Kbyte/32 Kword 14 Mbit Twenty-eight 64 Kbyte/32 Kword A29DL163 4 Mbit Eight 8 Kbyte/4 Kword, seven 64 Kbyte/32 Kword 12 Mbit Twenty-four 64 Kbyte/32 Kword A29DL164 8 Mbit Eight 8 Kbyte/4 Kword, fifteen 64 Kbyte/32 Kword 8 Mbit Sixteen 64 Kbyte/32 Kword |
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