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MB91F368GA Datasheet(PDF) 8 Page - Fujitsu Component Limited. |
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MB91F368GA Datasheet(HTML) 8 Page - Fujitsu Component Limited. |
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8 / 62 page  FME / EMDC / Br+JR - mb91f367g_f368g_ds.fm 8 10-Apr-01 1.3 Core Functionality Function Feature Remarks FR50 Core 32-bit Fujitsu RISC Core FR30 software compatible Clock module (clock control, clock divider, PLLs) Setting of frequencies for CPU and peripherals (see MB91FV360GA) Low power consumption modes: RTC mode: only the Real Time Clock and the selected oscillator are active (= STOP mode and bit 0 of STCR is set to 0) STOP mode: all internal circuits and the oscillation circuits are halted Watchdog adjustable watchdog timer interval (between 220 and 226 system clock cycles) I-RAM 4 kB I-RAM see remark below table D-bus RAM 16 kB RAM for user data see remark below table F-bus RAM 16 kB RAM for data and code see remark below table Flash Memory 512 kB sector architecture: sector 0: 64 kB | sector 7: 64 kB sector 1: 64 kB | sector 8: 64 kB sector 2: 64 kB | sector 9: 64 kB sector 3: 32 kB | sector 10: 32 kB sector 4: 8 kB | sector 11: 8 kB sector 5: 8 kB | sector 12: 8 kB sector 6: 16 kB | sector 13: 16 kB | | V V 16 bit 16 bit write access is 16 bit wide, read access can be 16 or 32 bit wide connected to F-Bus Minimum 10000 program/erase cycles Minimum 10 years data retention Net read cycle time to the memory is 40nS. For overall access time see settings in Chapter 2.1 Boot ROM 2 kB DMA 5 channels up to 16 DMA sources can be used transfer modes: single/block, burst, continuous |
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Similar Description - MB91F368GA |
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