EDE1104AASE datasheet(7/65 Pages) ELPIDA

Part #	EDE1104AASE

Description	1G bits DDR2 SDRAM organized as 33,554,432 words x 8 banks.

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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7 / 65 page

EDE1104AASE, EDE1108AASE

Data Sheet E0404E20 (Ver. 2.0)

7

DC Characteristics 1 (TC = 0

°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)

max.

Parameter

Symbol

Grade

× 4

× 8

Unit

Test condition

Operating current

(ACT-PRE)

IDD0

-6E

-5C

-4A

TBD

95

TBD

mA

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(ACT-READ-PRE)

IDD1

-6E

-5C

-4A

TBD

105

TBD

mA

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Precharge power-

down standby current

IDD2P

-6E

-5C

-4A

TBD

12

TBD

mA

all banks idle;

tCK = tCK (IDD);

CKE is L;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Precharge quiet

standby current

IDD2Q

-6E

-5C

-4A

TBD

35

TBD

mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Idle standby current

IDD2N

-6E

-5C

-4A

TBD

45

TBD

mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD3P-F

-6E

-5C

-4A

TBD

45

TBD

mA

Fast PDN Exit

MRS (12) = 0

Active power-down

standby current

IDD3P-S

-6E

-5C

-4A

TBD

20

TBD

mA

all banks open;

tCK = tCK (IDD);

CKE is L;

Other control and address

bus inputs are STABLE;

Data bus inputs are

FLOATING

Slow PDN Exit

MRS (12) = 1

Active standby

current

IDD3N

-6E

-5C

-4A

TBD

90

TBD

mA

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(Burst read operating)

IDD4R

-6E

-5C

-4A

TBD

190

TBD

mA

all banks open, continuous burst reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Operating current

(Burst write

operating)

IDD4W

-6E

-5C

-4A

TBD

190

TBD

mA

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

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