10-Bit Bus LVDS Deserializers

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9

into high impedance but LOCK continues to reflect the

status of the serial input. Driving REN high again

enables the ROUT_ and RCLK drivers.

Losing Lock on Serial Data

If one embedded clock edge (rising edge formed by

end/start bits) is not detected, LOCK goes high, RCLK

tracks REFCLK, and ROUT_ stays active but with

invalid data. LOCK stays high for a minimum of two

RCLK cycles. Then, if transitions are detected at the

serial input, the PLL attempts to lock to the serial input.

When the PLL locks to serial input data, LOCK goes

low, RCLK tracks the serializer reference clock (TCLK),

and ROUT_ is valid on the second selected strobe

edge of RCLK after LOCK goes low. A minimum of two

embedded clock edges in a row are required to regain

lock to the serial input after LOCK goes high.

For automatic resynchronization, LOCK can be con-

nected to the MAX9205/MAX9207 serializer SYNC1 or

SYNC2 input. With this connection, when LOCK goes

high, the serializer sends sync patterns until the deseri-

alizer locks to the serial input and drives LOCK low.

Input Fail-Safe

When the serial input is undriven (a disconnected cable

or serializer output in high impedance, for example) an

on-chip fail-safe circuit (Figure 2) drives the serial input

high. The response time of the fail-safe circuit depends

on interconnect characteristics. With an undriven input,

LOCK may switch high and low until the fail-safe circuit

takes effect. The undriven condition of the link can be

detected in spite of LOCK switching since LOCK is

high long enough to be sampled (LOCK is high for at

least two RCLK cycles after a missed clock edge and

RCLK keeps running, allowing sampling). If it is

required that LOCK remain high for an undriven input,

the on-chip fail-safe circuit can be supplemented with

external pullup bias resistors.

Deserializer Jitter Tolerance

jitter the deserializer can tolerate before a sampling

error occurs (Figure 9). Zero-to-peak jitter is measured

from the mean value of the deterministic jitter distribu-

tion. Sources of jitter include the serializer (supply

noise, reference clock jitter, pulse skew, and intersym-

bol interference), the interconnect (intersymbol interfer-

ence, crosstalk, within-pair skew, ground shift), and the

deserializer (supply noise). The sum of the zero-to-peak

individual jitter sources must be less than or equal to

For example, at 40MHz, the MAX9205 serializer has

140ps (p-p) maximum deterministic output jitter. The

zero-to-peak value is 140ps/2 = 70ps. If the intercon-

nect jitter is 100ps (p-p) with a symmetrical distribution,

the zero-to-peak jitter is 50ps. The MAX9206 deserializ-

er jitter tolerance is 720ps at 40MHz. The total zero-to-

peak input jitter is 70ps + 50ps = 120ps, which is less

than the jitter tolerance. In this case, the margin is

720ps - 120ps = 600ps.

REFCLK

FREQUENCY

16MHz

35MHz

40MHz

40MHz

DATA

PATTERN

PSEUDORANDOM

DATA

PSEUDORANDOM

DATA

PSEUDORANDOM

DATA

SYNC

PATTERNS

Maximum

0.749µs

0.375µs

0.354µs

0.134µs

Maximum (Clock

Cycles)

11.99

13.14

14.18

5.37

Average

0.318µs

0.158µs

0.144µs

0.103µs

Average (Clock

Cycles)

5.09

5.52

5.76

4.11

Minimum

0.13µs

0.068µs

0.061µs

0.061µs

Minimum (Clock

Cycles)

2.08

2.37

2.44

2.45

Table 1. Typical Lock Times

Note: Pseudorandom lock performed with 215-1 PRBS pattern, 10,000 lock time tests.