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MAX9208EAI Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX9208EAI Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 12 page 10-Bit Bus LVDS Deserializers ______________________________________________________________________________________ 11 Topologies The MAX9206/MAX9208 deserializers can operate in a variety of topologies. Examples of double-terminated point-to-point and point-to-point broadcast are shown in Figures 10 and 11. Use 1% surface-mount termina- tion resistors. A point-to-point interface terminated at each end in the characteristic impedance of the cable or PC board traces is shown in Figure 10. The total load seen by the serializer is 50 Ω. The double termination typically reduces reflections compared to a single 100 Ω termi- nation. A single 100 Ω termination at the deserializer input is feasible and makes the differential signal swing larger. A point-to-point version of a multidrop bus is shown in Figure 11. The low-jitter MAX9150 10-port repeater is used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. Compared to a bus, more interconnect is traded for robust hot-plug capability. The repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer con- nections. Since repeater jitter is a component of the total jitter seen at the deserializer input (along with other sources of jitter), a low-jitter repeater is essential in most high data-rate applications. Board Layout A four-layer PC board providing separate power, ground, and signal layers is recommended. Keep the LVTTL/LVCMOS inputs and outputs separated from the BLVDS inputs to prevent coupling into the BLVDS lines. Chip Information TRANSISTOR COUNT: 9602 PROCESS: CMOS LOGIC INPUTS REN PWRDN CONDITIONS OUTPUTS X Low Power applied and stable Power-down mode. PLL is stopped. Current consumption is reduced to 400µA (typ). ROUT_, RCLK, and LOCK are high impedance. Low High Deserializer initialized RCLK and ROUT_ are high impedance. LOCK is active, indicating the serial input status. High High Deserializer initialized RCLK and ROUT_ are active. LOCK is active, indicating the serial input status. Table 2. Input/Output Function Table X = don’t care 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 DVCC ROUT9 DGND DVCC DGND ROUT5 ROUT6 ROUT7 ROUT8 DGND AGND AGND AVCC LOCK RCLK REN PWRDN RI- RI+ AVCC REFCLK RCLK_R/F AGND SSOP TOP VIEW MAX9206/ MAX9208 Pin Configuration |
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