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SM79108 Datasheet(PDF) 10 Page - SyncMOS Technologies,Inc

Part No. SM79108
Description  8-Bit Micro-controller with 8KB flash & 256 Bytes RAM embedded
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Maker  SYNCMOS [SyncMOS Technologies,Inc]
Homepage  http://www.syncmos.com.tw
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 10 page
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January 2003
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
If user use Fosc=20MHz, SPFS[1:0] of SPWMC=#03H, then
SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz
SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
5. PWM Function Description:
Each PWM channel contains a 8-bit wide PWM data register (PWMDR) to decide number of continuous pulses within a
PWM frame cycle. The value programmed in the register will determine the pulse length of the output. The PWM channel
can be configured as 5-bit or 8-bit resolution. If a channel is configured as 5-bit resolution, only LSB 5 bits are available.
The value of each PWM Data Register (PWMDR) is continuously compared with the content of an internal counter to deter-
mine the state of each PWM channel output pin.
5.1 PWM Registers - PWMC0, PWMD0
PWM Registers - PWM Control Register (PWMC0, 0D3H)
PFS[1:0]: These two bits is 2’s power parameter to form a frequency divider for input clock.
PBS: This bit decides channel bit resolution. If PBS is set, the channel is 5-bit resolution.
Example : If user use Fosc = 20MHz, PFS[1:0] of PWMC = #03H, PBS = 0, then
PWM Clock = 20MHz / 128 = 156.25KHz
PWM Output cycle frame frequency = 156.25KHz / 256 = 610 Hz
Note : For bzzer application
bit-7
bit-0
Unused
Unused
Unused
Unused
Unused
PBS
PFS1
PFS0
Read / Write:
-
-
-
-
-
R/W
R/W
R/W
Reset value:
*
*
*
*
*
0
0
0
PFS1
PFS0
Divider
PWM clock, Fosc=12MHz
PWM clock, Fosc=24MHz
0
0
16
750KHz
1.5MHz
0
1
32
375KHz
750KHz
1
0
64
187.5KHz
375KHz
1
1
128
93.75KHz
187.5KHz
16T
16T
16T
16T
16T
16T
16T
16T
32T
32T
32T
32T
32T
32T
32T
32T
1st cycle frame 2nd cycle frame 3rd cycle frame
4th cycle frame 5th cycle frame
6th cycle frame 7th cycle frame
8th cycle frame
1T
1T
1T
SPWM clock = 1 / T = Fosc / 2^(SPFS[1:0]+1)
(narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(SPFS[1:0]+1)]/32




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