MSC2343257A-xxBS8/DS8

¡ Semiconductor

108

See ADDENDUM I for AC Timing Waveforms

Notes:

1. A start-up delay of 200

µs is required after power-up, followed by a minimum of eight

initializationcycles(RAS-onlyrefreshorCASbefore RAS refresh)beforeproperdevice

operation is achieved.

4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.

the open circuit condition and are not referenced to output voltage levels.

10. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.

This mode is latched and remains in effect until the exit cycle is generated.

The test mode specified in this data sheet is an 8-bit parallel test function. CA0, CA1

and CA10 are not used. In a read cycle, if all internal bits are equal, the DQ pin will

indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low

level. The test mode is cleared and the memory device returned to its normal

operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh

cycle.

The 4M ¥ 32 module can be tested as an 1M ¥ 32 module in this test mode.

11. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test

mode parameters are obtained by adding 5 ns to the normal read cycle values.