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SCD128410QCE Datasheet(PDF) 3 Page - Intel Corporation |
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SCD128410QCE Datasheet(HTML) 3 Page - Intel Corporation |
3 / 176 page Datasheet 3 IEEE 1284-Compatible Parallel Interface Controller — CD1284 Contents 1.0 Overview ......................................................................................................................12 2.0 Conventions ...............................................................................................................15 2.1 Abbreviations....................................................................................................... 15 2.2 Acronyms ............................................................................................................15 3.0 Pin Information..........................................................................................................17 3.1 Pin Diagram......................................................................................................... 17 3.2 Pin List................................................................................................................. 18 4.0 Register Summary ...................................................................................................24 4.1 Register Summary Tables................................................................................... 24 4.2 Register Usage.................................................................................................... 27 5.0 Functional Description...........................................................................................31 5.1 Device Architecture ............................................................................................. 31 5.2 CPU Interface......................................................................................................33 5.2.1 Read Cycles ........................................................................................... 33 5.2.2 Write Cycles ........................................................................................... 34 5.2.3 Service-Acknowledge Cycles ................................................................. 34 5.2.4 DMA Cycles............................................................................................ 34 5.3 Serial Port Service Requests .............................................................................. 35 5.3.1 Interrupts ................................................................................................ 36 5.3.2 DMAREQ* as Parallel Interrupt Source..................................................36 5.3.3 Serial Service Request Polling ...............................................................40 5.3.4 Daisy-Chaining Service Requests with CD1400s .................................. 41 5.4 Parallel Port Service Requests............................................................................43 5.4.1 Hardware-Activated Context Switch, Parallel......................................... 48 5.4.2 Software-Activated Context Switch, Parallel .......................................... 49 5.5 Serial Data Reception and Transmission ............................................................ 49 5.5.1 Receiver Operation ................................................................................ 50 5.5.2 Receiver Timer Operations .................................................................... 51 5.5.3 Receive Exceptions................................................................................ 52 5.5.4 Transmitter Operation ............................................................................54 5.6 Flow Control ........................................................................................................ 55 5.6.1 In-Band Flow Control.............................................................................. 55 5.6.2 Receiver In-Band Flow Control .............................................................. 55 5.6.3 Out-of-Band Flow Control....................................................................... 58 5.6.4 Modem Signals and General-Purpose I/O ............................................. 59 5.7 Receive Special Character Processing ...............................................................61 5.7.1 UNIX‚ Character Processing .................................................................. 61 5.7.2 Non-UNIX‚ Receive Special Character Processing ................................ 63 5.8 Transmit Special Character Processing .............................................................. 67 5.8.1 Line Terminating Characters .................................................................. 67 5.8.2 Embedded Transmit Commands............................................................ 67 5.8.3 Send Special Character Command ........................................................ 68 5.9 Baud Rate Generation.........................................................................................72 |
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