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XRT71D04IV Datasheet(PDF) 5 Page - Exar Corporation |
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XRT71D04IV Datasheet(HTML) 5 Page - Exar Corporation |
5 / 22 page áç áç áç áç XRT71D04 4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER REV. 1.1.1 4 12 MODE_CTRL I Mode Control: When “High” in Multimode, all channels are independent. When “Low”, the Mas- ter Channel (channel_0) controls DS3/E3_n, STS1_n, RCLKES, FSS and MCLK_n. DJA is NOT affected. Internal 50 K Ohm pull-up resistor. 13 ICT I In Circuit Testing Input. (Active low): With this pin tied to ground, all output pins will be in high impedance mode for in- circuit-testing. For normal operation this input pin should be tied to VDD. Internal 50 K Ohm pull-up resistor. 14 HOST I Host/Hardware Mode Select: An active-high input enables the Host mode. Data is written to the command reg- isters to configure the XRT71D04. In the Host mode, the states of discrete input pins are inactive. An active-low input enables the Hardware Mode.In this mode, the discrete inputs are active. Internal 50 K Ohm pull-down resistor. 15 FLRST I FIFO Limit Reset Hardware Mode Whenever the FIFO is within 2 bits of either underflow or overflow, the FL_n will be set high. This pin allows the user to reset the state of FL_n, (FIFO Limit) output pin. This pin when pulsed “High”, resets the the FL_n output pin, (toggles to GND). NOTE: The FL_n could be set “High” again if the FIFO is within 2 bits of either underflow or overflow. Host Mode Reading the FL_n bits in the status registers clears this FL_n pin. Master Reset also clears the FL_n output. This pin is tied to GND. FLRST has no effect in this mode. Internal 50 K Ohm pull-down resistor. 16 RRNEG_3 O Received Recovered Negative Data (De-Jittered) Output - channel 3: See description of pin 6 17 RRPOS_3 O Received Positive Data (De-Jittered) Output - channel 3: See description of pin 5 18 RRCLK_3 O Received Recovered Output (De-jittered) Clock - channel 3: See description of pin 4 19 GND O Digital Ground 20 AVDD **** Analog Power Supply = 5V±5% or 3.3V±5% 21 AGND **** Analog Ground 22 FL_0 O FIFO Limit - channel 0: This output pin is driven high whenever the internal FIFO comes within two-bits of being either underflow or overflow. PIN DESCRIPTION PIN #NAME TYPE DESCRIPTION |
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