December 22, 2003
Document No. 38-12009 Rev. *D
9
CY8C22xxx Preliminary Data Sheet
Contents
18.2.7
CLK_CR1 Register.......................................................................................230
18.2.8
AMD_CR1 Register......................................................................................230
18.2.9
ALT_CR0 Register .......................................................................................230
19. Analog Array ........................................................................................................ 231
19.1
Architectural Description ....................................................................................................231
19.1.1
Analog Comparator Bus...............................................................................233
19.2
Temperature Sensing Capability........................................................................................233
20. Analog Input Configuration ................................................................................... 235
20.1
Register Definitions ............................................................................................................235
20.1.1
AMX_IN Register .........................................................................................235
20.1.2
ABF_CR0 Register.......................................................................................235
20.2
Architectural Description ....................................................................................................236
21. Analog Reference ................................................................................................. 237
21.1
Architectural Description ....................................................................................................237
21.2
Register Definitions ............................................................................................................238
21.2.1
ARF_CR Register ........................................................................................238
22. Switched Capacitor Block ..................................................................................... 239
22.1
Architectural Description ...................................................................................................240
22.2
Application Description.......................................................................................................241
22.3
Register Definitions ............................................................................................................241
22.3.1
ASCxxCR0 Register.....................................................................................242
22.3.2
ASCxxCR1 Register.....................................................................................242
22.3.3
ASCxxCR2 Register.....................................................................................242
22.3.4
ASCxxCR3 Register.....................................................................................243
22.3.5
ASDxxCR0 Register.....................................................................................243
22.3.6
ASDxxCR1 Register.....................................................................................243
22.3.7
ASDxxCR2 Register.....................................................................................243
22.3.8
ASDxxCR3 Register.....................................................................................244
23. Continuous Time Block ......................................................................................... 245
23.1
Architectural Description ....................................................................................................245
23.2
Register Definitions ............................................................................................................247
23.2.1
ACBxxCR0 Register.....................................................................................247
23.2.2
ACBxxCR1 Register.....................................................................................247
23.2.3
ACBxxCR2 Register.....................................................................................247
23.2.4
ACBxxCR3 Register.....................................................................................247
SECTION F SYSTEM RESOURCES
251
Top-Level System Resources Architecture ....................................................................................251
System Resources Register Summary ..........................................................................................252
24. Digital Clocks ....................................................................................................... 253
24.1
Architectural Description ....................................................................................................253
24.1.1
Internal Main Oscillator ................................................................................253
24.1.2
Internal Low Speed Oscillator ......................................................................254
24.1.3
32 kHz Crystal Oscillator..............................................................................254