December 22, 2003
Document No. 38-12009 Rev. *D
5
CY8C22xxx Preliminary Data Sheet
Contents
9.
Internal Low Speed Oscillator (ILO) ........................................................................65
9.1
Architectural Description ......................................................................................................65
9.2
Register Definitions ..............................................................................................................65
9.2.1
ILO_TR Register ............................................................................................65
10. 32 kHz Crystal Oscillator (ECO) ..............................................................................67
10.1
Architectural Description ......................................................................................................67
10.1.1
ECO External Components............................................................................68
10.2
Register Definitions ..............................................................................................................68
10.2.1
OSC_CR0 Register........................................................................................68
10.2.2
ECO_TR Register ..........................................................................................69
10.2.3
CPU_SCR1 Register......................................................................................69
11. Phase Locked Loop (PLL) ....................................................................................... 71
11.1
Architectural Description ......................................................................................................71
11.2
Register Definitions ..............................................................................................................71
11.2.1
OSC_CR0 Register........................................................................................71
11.2.2
OSC_CR2 Register........................................................................................72
12. Sleep and Watchdog .............................................................................................. 73
12.1
Architectural Description ......................................................................................................73
12.1.1
32 kHz Clock Selection ..................................................................................73
12.1.2
Sleep Timer ....................................................................................................74
12.1.3
Sleep Bit.........................................................................................................74
12.2
Application Description.........................................................................................................74
12.3
Register Definitions ..............................................................................................................75
12.3.1
INT_MSK0 Register .......................................................................................75
12.3.2
RES_WDT Register .......................................................................................75
12.3.3
OSC_CR0 Register........................................................................................75
12.3.4
CPU_SCR1 Register......................................................................................76
12.3.5
ILO_TR Register ............................................................................................76
12.3.6
ECO_TR Register ..........................................................................................76
12.3.7
CPU_SCR0 Register......................................................................................76
12.4
Timing Diagrams ..................................................................................................................77
12.4.1
Sleep Sequence.............................................................................................77
12.4.2
Wake Up Sequence .......................................................................................78
12.4.3
Bandgap Refresh ...........................................................................................79
12.4.4
Watchdog Timer (WDT) .................................................................................79
12.5
Power Consumption .............................................................................................................80
SECTION C REGISTER REFERENCE
81
Register Conventions .......................................................................................................................81
Register Mapping Tables .................................................................................................................81
Register Map 0 Table: User Space ..............................................................................82
Register Map 1 Table: Configuration Space ................................................................83
13. Register Details ...................................................................................................... 85
13.1
Bank 0 Registers..................................................................................................................86
13.1.1
PRTxDR ........................................................................................................86
13.1.2
PRTxIE ..........................................................................................................87
13.1.3
PRTxGS ........................................................................................................88
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