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CY29942
Document #: 38-07284 Rev. *B
Page 4 of 7
Notes:
5.
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6.
Outputs driving 50
Ω transmission lines.
7.
See Figure 1.
8.
50% input duty cycle.
9.
Across temperature and voltage ranges, includes output skew.
10. For a specific temperature and voltage, includes output skew.
AC Parameters[5]: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, Over the specified temperature range
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Input Frequency
200
MHz
Tpd
TTL_CLK to Q Delay[6, 7]
VDD = 3.3V
1.8
3.3
3.8
ns
VDD = 2.5V
2.3
3.8
4.4
FoutDC
Output Duty Cycle[6, 7, 8]
Measured at VDD/2
45
55
%
Tskew
Output-to-Output Skew[6, 7]
200
ps
Tskew(pp)
Part-to-Part Skew[9]
VDD = 3.3V
1.0
ns
VDD = 2.5V
1.3
Tskew(pp)
Part-to-Part Skew[10]
600
ps
Tr/Tf
Output Clocks Rise/Fall
Time[6, 7]
0.8V to 2.0V, VDD = 3.3V
0.2
1.1
ns
0.5V to 1.8V, VDD = 2.5V
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
Zo = 50 ohm
VTT
RT = 50 ohm
RT = 50 ohm
CY29942 DUT
Figure 1. LVCMOS_CLK CY29942 Test Reference for VCC = 3.3V and VCC = 2.5V
tPD
LVCMOS_CLK
Q
VCC
GND
VCC /2
VCC
GND
VCC /2
Figure 2. LVCMOS Propagation Delay (TPD) Test Reference
VCC
GND
VCC /2
tP
T0
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (FoutDC)
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