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IC61C6416-20K Datasheet(PDF) 1 Page - Integrated Circuit Solution Inc |
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IC61C6416-20K Datasheet(HTML) 1 Page - Integrated Circuit Solution Inc |
1 / 10 page .EATURES High-speed access time: 10, 12, 15, and 20 ns CMOS low power operation 1650 mW (max) @ -10ns Cycle 55 mW (max) CMOS Standby TTL compatible interface levels Single 5V ± 10% power supply .ully static operation: no clock or refresh required Three state outputs Industrial temperature available Available in 44-pin SOJ package and 44-pin TSOP-2 1+$+$"$ 64K x 16 HIGH-SPEED CMOS STATIC RAM DESCRIPTION The 1+51 IC61C6416 is a high-speed, 1,048,576-bit static RAM organized as 65,536 words by 16 bits. It is fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC61C6416 is packaged in the JEDEC standard 44-pin 400mil SOJ and 44-pin 400mil TSOP-2. .UNCTIONAL BLOCK DIAGRAM ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. A0-A15 CE OE WE 64K x 16 MEMORY ARRAY DECODER COLUMN I/O CONTROL CIRCUIT GND VCC I/O DATA CIRCUIT I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte UB LB Integrated Circuit Solution Inc. 1 AHSR011-0A 05/23/2001 |
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