DS3148N datasheet(9/89 Pages) MAXIM

Part #	DS3148N

Description	6-/8-/12-Channel DS3/E3 Framers

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Manufacturer	MAXIM [Maxim Integrated Products]

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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers

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5. PIN DESCRIPTION

5.1 Transmit Formatter LIU Interface Pins

NAME

TYPE

FUNCTION

TPOS/

TNRZ

O

Transmit Positive Data Output/Transmit NRZ Data Output. If BIN = 0 in the MC1 register, the LIU interface

is in dual-rail (POS/NEG) mode. In this mode, the transmit formatter outputs the serial data stream in

alternate mark inversion (AMI) format. TPOS = 1 signals an external LIU to drive a positive pulse on the

line, while TNEG = 1 tells the LIU to drive a negative pulse on the line. If BIN = 1, the LIU interface is in

binary (NRZ) mode. In this mode, the transmit formatter outputs the serial data stream in binary format on

the TNRZ pin. TNRZ = 1 indicates a 1 in the data stream, while TNRZ = 0 indicates a 0. If TCLKI = 0 in the

MC5 register, data is clocked out of the formatter on the rising edge of TCLK. If TCLKI = 1, data is clocked

out on the falling edge of TCLK. MC5:TPOSH = 1 forces TPOS/TNRZ high. MC5:TPOSI = 1 inverts the

polarity of TPOS/TNRZ. Setting both TPOSH = 1 and TPOSI = 1 forces TPOS/TNRZ low.

TNEG

O

Transmit Negative Data Output. If BIN = 0 in the MC1 register, the LIU interface is in dual-rail (POS/NEG)

mode. In this mode, the transmit formatter outputs the serial data stream in AMI format. TPOS = 1 signals

an external LIU to drive a positive pulse on the line, while TNEG = 1 tells the LIU to drive a negative pulse

on the line. If BIN = 1, the LIU interface is in binary (NRZ) mode. In this mode the transmit formatter outputs

the serial data stream in binary format on the TNRZ pin, and TNEG is driven low. If TCLKI = 0 in the MC5

register, data is clocked out of the formatter on the rising edge of TCLK. If TCLKI = 1, data is clocked out on

the falling edge of TCLK. MC5:TNEGH = 1 forces TNEG high. MC5:TNEGI = 1 inverts the polarity of TNEG.

Setting both TNEGH = 1 and TNEGI = 1 forces TNEG low.

TCLK

O

Transmit Clock Output. TCLK is used to clock data out of the transmit formatter on TPOS/TNEG (dual-rail

LIU interface mode) or TNRZ (binary LIU interface mode). If TCLKI = 0 in the MC5 register, data is clocked

out of the formatter on the rising edge of TCLK. If TCLKI = 1, data is clocked out on the falling edge of

TCLK. TCLK is normally a buffered (and optionally inverted) version of TICLK. When either line loopback or

payload loopback is active, TCLK is a buffered (and optionally inverted) version of RCLK. When a clock is

not present on TICLK and MC1:LOTCMC = 1, TCLK is a buffered (and optionally inverted) version of

RCLK.

5.2 Receive Framer LIU Interface Pins

NAME

TYPE

FUNCTION

RPOS/

RNRZ

I

Receive Positive Data Input/Receive NRZ Data Input. If BIN = 0 in the MC1 register, the LIU interface is in

dual-rail (POS/NEG) mode. In this mode, the framer clocks in the serial data stream in AMI format. RPOS =

1 from an external LIU indicates a positive pulse was received on the line; RNEG = 1 from the LIU indicates

a negative pulse was received on the line. If BIN = 1, the framer is in binary (NRZ) LIU interface mode. In

this mode the framer clocks in the serial data stream in binary format on the RNRZ pin. RNRZ = 1 indicates

a 1 in the data stream; RNRZ = 0 indicates a 0 in the data stream. If RCLKI = 0 in the MC5 register, data is

clocked into the framer on the rising edge of RCLK. If RCLKI = 1, data is clocked in on the falling edge of

RCLK. MC5:RPOSI = 1 inverts the polarity of RPOS/RNRZ.

RNEG/

RLCV

I

Receive Negative Data Input/Receive Line-Code Violation Input. If BIN = 0 in the MC1 register, the LIU

interface is in dual-rail (POS/NEG) mode. In this mode, the framer clocks in the serial data stream in AMI

format. RPOS = 1 from an external LIU indicates a positive pulse was received on the line, while RNEG = 1

from the LIU indicates a negative pulse was received on the line. If BIN = 1, the framer is in binary (NRZ)

LIU interface mode. In this mode the framer clocks in the serial data stream in binary format on the RNRZ

pin and line code violations on the RLCV pin. If RCLKI = 0 in the MC5 register, data is clocked into the

framer on the rising edge of RCLK. If RCLKI = 1, data is clocked in on the falling edge of RCLK.

MC5:RNEGI = 1 inverts the polarity of RNEG/RLCV. In binary LIU interface mode, when MC5:RNEGI = 0,

the BPV counter (registers BPVCR1 and BPVCR2) counts RCLK cycles when RLCV = 1. When

MC5:RNEGI = 1, the BPV counter counts RCLK cycles when RLCV = 0.

RCLK

I

Receive Clock Input. RCLK is used to clock data into the receive framer on RPOS/RNEG (dual-rail LIU

interface mode) or RNRZ (binary LIU interface mode). If RCLKI = 0 in the MC5 register, data is clocked into

the framer on the rising edge of RCLK. If RCLKI = 1, data is clocked in on the falling edge of RCLK. RCLK is

normally accurate to within ±20ppm when sourced from an LIU, but the framer can also accept a gapped

clock up to 52MHz on RCLK, such as those commonly sourced from ICs that map/demap DS3 and E3

to/from SONET/SDH.

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