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FPD33584 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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FPD33584 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 30 page  Functional Description (Continued) nematic (TN) display with a 2.2 gamma transfer character- istic. Additional, custom gamma curves can be requested through your National Semiconductor representative. A typi- cal TN display, when operated with the FPD33584 drivers will produce a luminance with grayscale characteristic typical of CRT monitors. The resistor values for all R-DACs are shown in Figure 22. The individual R-DAC characteristics can be found in: • Gamma A — Figure 4, Figure 5, and Figure 6 • Gamma B — Figure 7, Figure 8, and Figure 9 • Gamma C — Figure 10, Figure 11, and Figure 12 • Gamma D — Figure 13, Figure 14, and Figure 15 • Gamma F — Figure 16, Figure 17, and Figure 18 • Gamma G — Figure 19, Figure 20, and Figure 21 Most applications will only need to provide references for each of the two ends of the two R-DACs (GMA1, GMA5, GMA6, and GMA10). Six additional, intemediate R-DAC tap points are available for further customization. CHARGE CONSERVATION TECHNOLOGY National Semiconductor’s proprietary charge conservation technology significantly reduces power consumption. Charge conservation works by briefly switching all of the columns to a common node at the start of each line. This has the effect of redistributing the charge stored in the capaci- tance of the panel columns. Because half the columns are at voltages more positive than V com and half are more nega- tive, this redistribution of charge or “charge-sharing” has the effect of pulling all of the columns to a neutral voltage near the middle of the driver’s dynamic range. Thus, the voltages on all the columns are driven approximately halfway toward their next value with no power expended. This dramatically reduces panel power dissipation (up to a theoretical limit of 50%) compared to conventional drivers which must drive each column through the entire voltage swing every time polarity is reversed. ’Smart’ charge sharing is used to further optimize this fea- ture. Data inversion is monitored and charge shared only across data ranges (when output polarity changes between adjacent lines). This is useful during n-line inversion when polarity changes do not occur at every line transition. TABLE 1. Charge Sharing Definition TIME0 TIME1 Charge Share Time 0 0 16 RSDS CLKs (approx. 250ns @ 65MHz) 0 1 32 RSDS CLKs (approx. 500ns @ 65MHz) 1 0 64 RSDS CLKs (approx. 1µs @ 65MHz) 1 1 128 RSDS CLKs (approx. 2µs @ 65MHz) As shown in Figure 3, charge sharing begins at the falling edge of CLK1 and continues for the number or RSDS clock cycles shown in Table 1. For more information on National’s proprietary Smart Charge Sharing technology, please see application note AN1235 Using Smart Charge Sharing to Reduce Power and Boost Column Driver Performance, which is available on the National Semiconductor website or through your National Semiconductor representative. The amount of charge share time is determined by 2 pins: TIME0 and TIME1. Both TIME0 and TIME1 pins default to a low state, so if both pins are left floating, the charge share time will be 16 RSDS clock cycles. For most applications, one of the charge share times defined by TIME0 and TIME1 will optimize the performance and power savings in the panel. Generally, the average panel should set charge shar- ing at either 32 RSDS clocks or 64 RSDS clocks, depending on the data rate and the panel load. Panels with much larger RC loads may need to increase the charge share time to get the maximum benefit and panels with a smaller load can realize power savings with a shorter charge share time. Please contact National Semiconductor if you need further assistance in selecting a charge share time. RSDS DATA CHANNEL The RSDS data bus is comprised of nine channels and a common clock. Each channel consists of a two wire differ- ential pair. The nine channels carry digital video data orga- nized as three busses of three channels. Each three channel bus corresponds on one of the three video colors, red, green and blue. The three video busses are comprised of a most, middle and least significant bit. The six bit video word is carried on the three wires of each video bus in two consecu- tive half words. The even fields of the word are transmitted- received on a first clock and are followed by the odd fields on the following clock transition. Clocking is dual edge and the clock signal is also carried on a two wire, differential pair. OPTIONAL REPAIR AMPLIFIERS The FPD33584 provides two general purpose, unity gain output buffers, one located at each end of the input bank of the die. These buffers may be used to repair an open in a column line. The drive signal from the output of the faulted line can be stitched to the input of the repair buffer during the repair process. The output of the repair buffer is then routed to the other side of the column line making it possible to maintain fast rise and fall times on both ends of the afflicted column line. PIN DESCRIPTIONS The pin order configuration for the FPD33584 is shown in Figure 23 CLKP and CLKN — Data Clock (input) Differential clock input for RSDS data loading. D00P–D22N — RSDS Data Bus (input) D0xP–D0xN — Data for OUTPUTS 1,4,7...382 (red) D1xP–D1xN — Data for OUTPUTS 2,5,8...383 (green) D2xP–D2xN — Data for OUTPUTS 3,6,9...384 (blue) Wherex=0 (LSB), 1 or 2 (MSB). CLK1 — Data Load (input) The rising edge of CLK1 copies the digital video buffered by the shift register into a second latch for conversion to analog. The falling edge of CLK1 begins charge sharing. POL — Polarity (input) 20043216 FIGURE 3. FPD33584 Charge Share Timing www.national.com 8 |
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