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HT95C200 Datasheet(PDF) 8 Page - Holtek Semiconductor Inc |
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HT95C200 Datasheet(HTML) 8 Page - Holtek Semiconductor Inc |
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8 / 42 page  HT95L100/10P Rev. 0.10 8 October 1, 2002 Preliminary Stack register This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither read- able nor write-able. The activated level is indexed by the stack pointer (SP) and is neither readable nor write-able. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the pro- gram counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and an interrupt takes place, the interrupt request flag will be recorded but the acknowl- edge signal will be inhibited even if this interrupt is en- abled. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature pre- vents stack overflow allowing the programmer to use the structure more easily. If the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return addresses are stored). Data memory The data memory is divided into four functional groups: special function registers, embedded control register, LCD display memory and general purpose memory. Most are read/write, but some are read only. The special function registers is located from 00H to 1FH. The embedded control register are located in the memory areas from 20H to 3FH. The remaining space which are not specified on the following table before the 40H are reserved for future expanded usage and read- ing these locations will get ²00H². The general purpose data memory is divided into 6 banks. The banks in the RAM are all addressed from 40H to 0FFH and they are selected by setting the value of the bank pointer (BP). All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer registers (MP0 or MP1). The bank1~bank10 are only indirectly accessible through memory pointer 1 register (MP1). The LCD display memory is located at bank 1BH. They can be read and written to by the indirect addressing mode using memory pointer 1 (MP1). To turn the display On or Off, a ²1² or ²0² is written to the corresponding bit of the memory area. Special register, embedded control register, LCD display memory and general purpose RAM BP Address Function Description Special function register 00 00 IAR0 Indirect addressing register 0 00 01 MP0 Memory pointer register 0 00 02 IAR1 Indirect addressing register 1 00 03 MP1 Memory pointer register 1 00 04 BP Bank pointer register 00 05 ACC Accumulator 00 06 PCL Program counter lower-order byte register 00 07 TBLP Table pointer 00 08 TBLH Table higher-order byte register 00 09 WDTS Watchdog Timer option setting register 00 0A STATUS Status register 00 0B INTC0 Interrupt control register 0 00 0C TMR0H Timer/Event Counter 0 high-order byte register 00 0D TMR0L Timer/Event Counter 0 low-order byte register 00 0E TMR0C Timer/Event Counter 0 control register 00 0F TMR1H Timer/Event Counter 1 high-order byte register 00 10 TMR1L Timer/Event Counter 1 low-order byte register |
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