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IDT72V90823PF Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT72V90823PF Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 27 page 5 COMMERCIALTEMPERATURERANGE IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 IM(1) CPU Interface Mode I When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor port is in non-multiplexed mode. AD0-7(1) Address/Data Bus I/O These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins 0 to 7 are also the input address bits of the microprocessor port. D8-15(1) Data Bus 8-15 I/O These pins are the eight most significant data bits of the microprocessor port. DTA(1) Data Transfer O This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin Acknowledgment drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is in high-impedance. CCO(1) Control Output O This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1,024 or 2.048 bits per frame respectively. The level of each bit is determined by the CCO bit in the connection memory. See External Drive Control Section. ODE(1) Output Drive Enable I This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15 output drivers are enabled. However, each channel may still be put into a high-impedance state by using the per channel control bit in the connection memory. PIN DESCRIPTION (CONTINUED) SYMBOL NAME I/O DESCRIPTION NOTE: 1. These pins are 5V tolerant. |
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