Multichannel, True-Differential,

Serial, 14-Bit ADCs

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5

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: Offset nulled. Measured with external reference.

Note 4: “On” channel grounded; full-scale 1kHz sine wave applied to all “off” channels.

Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. (See

Figures 8–11.)

Note 8: External load should not change during conversion for specified accuracy.

TIMING CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DIN to SCLK Setup Time

50

ns

DIN to SCLK Hold Time

0ns

SCLK Fall to Output Data Valid

10

80

ns

CS Fall to DOUT Enable

120

ns

CS Rise to DOUT Disable

120

ns

SHDN Rise CS Fall to SCLK Rise

Time

50

ns

SHDN Rise CS Fall to SCLK Rise

Hold Time

50

ns

External clock mode

0.1

2.1

SCLK Clock Frequency

Internal clock mode

0

2.1

MHz

SCLK Pulse-Width High

Internal clock mode

100

ns

SCLK Pulse-Width Low

Internal clock mode

100

ns

CS Fall to SSTRB Output Enable

External clock mode only

120

ns

CS Rise to SSTRB Output Disable

External clock mode only

120

ns

SSTRB Rise to SCLK Rise

Internal clock mode only

0

ns

SCLK Fall to SSTRB Edge

80

ns

CS Pulse Width

100

ns