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MSM514212 Datasheet(PDF) 7 Page - OKI electronic componets |
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MSM514212 Datasheet(HTML) 7 Page - OKI electronic componets |
7 / 15 page 7/15 ¡ Semiconductor MSM514212 SIGNAL DESCRIPTIONS Data Inputs (DIN0 - DIN7) Data on these inputs is shifted in on the rising edge of WCK while WE is held at a low level. The data setup and hold times tDS and tDH are referenced to the rising edge of WCK. Data Outputs (DOUT0 - DOUT7) Data is shifted out on these outputs during the rising edge of RCK while RE is held at a low level. The data becomes valid after the access time interval tAC which begins at the rising edge of RCK. Write Address Pointer Reset (WR) If WR is brought to a low level, the next rising edge of WCK resets the write address pointer to the first address location. The write address pointer is automatically reset when the last address location (5048) is clocked. The WR setup, and hold times tRS and tRH are referenced to the rising edge of WCK. Each write operation, which begins after WR, must contain at least 18 active write cycles, i.e. WCK cycles while WE is high. Read Address Pointer Reset (RR) If RR is brought to a low level, the next rising edge of RCK resets the read address pointer to the first address location. The read address pointer is automatically reset when the last address location (5048) is clocked. The RR setup, and hold times tRS and tRH are referenced to the rising edge of WCK. Each read operation, which begins after RR, must contain at least 18 active read cycles, i.e. RCK cycles while RE is high. Write Enable (WE) This pin is used as a gating function for the WCK input. If WE is held low, normal write cycles can occur. If WE is brought to a high level before the next rising edge of WCK, all subsequent write cycles will be inhibited, and the write address pointer remains unchanged. The WE setup and hold times tWES and tWEH are referenced to the rising edge of WCK. Read Enable (RE) This pin is used as a gating function for the RCK input. If RE is brought to a high level before the next rising edge of RCK, all subsequent read cycles are inhibited, and the read address pointer remains unchanged. The data outputs will tri-state after the output buffer turn off delay time tHZ, which begins at the rising edge of RCK. After the disabled cycles are completed, and the RE signal is brought back to a low level, the data output buffers are re-enabled by the next rising edge of RCK. The RE setup, and hold times tRES and tREH are referenced to the rising edge of RCK. Write Clock (WCK) The rising edge of the WCK input latches the data into the internal registers, and also increments the write address pointer when WE is held low. Read Clock (RCK) The rising edge of the RCK input shifts out the data from the internal registers and increments the read address pointer when RE is held low. |
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