Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

AM2404ITSA Datasheet(PDF) 5 Page - Anachip Corp

Part # AM2404ITSA
Description  2-Wire Serial 4K-Bit (512 x 8) CMOS Electrically Erasable PROM
Download  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ANACHIP [Anachip Corp]
Direct Link  
Logo ANACHIP - Anachip Corp

AM2404ITSA Datasheet(HTML) 5 Page - Anachip Corp

  AM2404ITSA Datasheet HTML 1Page - Anachip Corp AM2404ITSA Datasheet HTML 2Page - Anachip Corp AM2404ITSA Datasheet HTML 3Page - Anachip Corp AM2404ITSA Datasheet HTML 4Page - Anachip Corp AM2404ITSA Datasheet HTML 5Page - Anachip Corp AM2404ITSA Datasheet HTML 6Page - Anachip Corp AM2404ITSA Datasheet HTML 7Page - Anachip Corp AM2404ITSA Datasheet HTML 8Page - Anachip Corp AM2404ITSA Datasheet HTML 9Page - Anachip Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 12 page
background image
2-Wire Serial 4K-Bit (512 x 8) CMOS Electrically Erasable PROM
AM24LC04
Anachip Corp.
www.anachip.com.tw
Rev.A2 Oct 8, 2003
5/12
ATC
Functional Description (Continued)
Acknowledge
Each receiving device, when addressed, is obliged
to generate an acknowledge after the reception of
each byte. The master device must generate an
extra clock pulse which is associated with this
acknowledge bit. The device that acknowledges,
has to pull down the SDA line during the
acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by
not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable
the master to generate the STOP condition. (Shown
in Figure 3)
Devices Addressing
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit
device code (1010) for the AM24LC04, 3-bit device
address (A2 A1 A0) and 1-bit value indicating the
read or write mode. All I
2C EEPROMs use and
internal protocol that defines a PAGE BLOCK size of
4K bits. The eighth bit of slave address determines if
the master device wants to read or write to the
AM24LC04. (Refer to table B).
The
AM24LC04
monitor
the
bus
for
its
corresponding slave address all the time. It
generates an acknowledge bit if the slave address
was true and it is not in a programming mode.
Table B
Operation
Control Code
Chip
Select
R/W
Read
Write
1010
1010
A2 A1 A0
A2 A1 A0
1
0
A1, A2 are used to access device address for
AM24LC04; A0 is no connect.
Write Operations
Byte Write
Following the start signal from the master, the slave
address is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver that a byte with a word address will follow
after it has generated a acknowledge bit during the
ninth clock cycle.
Therefore the next byte transmitted by the master is
the word address and will be written into the address
pointer of the AM24LC04. After receiving another
acknowledge signal from the AM24LC04 the master
device will transmit the data word to be written into
the addressed memory location. The AM24LC04
acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this period the AM24LC04 will not
generate acknowledge signals. (Shown in Figure 4)
Page Write
The write control byte, word address and the first
data byte are transmitted to the AM24LC04 in the
same way as in a byte write. But instead of
generating a stop condition the master transmit up
to 16 data bytes to the AM24LC04 which are
temporarily stored in the on-chip page buffer and will
be written into the memory after the master has
transmitted a stop condition. After the receipt of
each byte, the four lower order address pointer bits
are internally incremented by one. The higher order
five bits of the word address remains constant. If the
master should transmit more than 16 bytes prior to
generating the stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once
the stop condition is received an internal write cycle
will begin. (Shown in Figure 5).
Acknowledge Polling
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle
is complete (this feature can be used to maximize
bus throughout). Once the stop condition for a write
command has been issued from the master, the
device initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves
the master sending a start condition followed by the
control byte for a write command (R/W = 0). If the
device is still busy with the write cycle , then no ACK
will returned. If the cycle is complete then the device
will return the ACK and the master can then proceed
with the next read or write commands.


Similar Part No. - AM2404ITSA

ManufacturerPart #DatasheetDescription
logo
Texas Instruments
AM2431 TI-AM2431 Datasheet
6Mb / 316P
[Old version datasheet]   AM243x Sitara??Microcontrollers
AM2431 TI-AM2431 Datasheet
5Mb / 242P
[Old version datasheet]   AM243x Sitara??Microcontrollers
MARCH 2022
AM2431 TI-AM2431 Datasheet
6Mb / 280P
[Old version datasheet]   AM243x Sitara™ Microcontrollers
REVISED AUGUST 2022
AM2431 TI-AM2431 Datasheet
6Mb / 282P
[Old version datasheet]   AM243x Sitara™ Microcontrollers
REVISED SEPTEMBER 2022
AM2431..ALV TI-AM2431..ALV Datasheet
6Mb / 280P
[Old version datasheet]   AM243x Sitara™ Microcontrollers
REVISED AUGUST 2022
More results

Similar Description - AM2404ITSA

ManufacturerPart #DatasheetDescription
logo
Anachip Corp
AM24LC08 ANACHIP-AM24LC08 Datasheet
202Kb / 10P
   2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM
logo
Integrated Silicon Solu...
IS93C56A ISSI-IS93C56A Datasheet
131Kb / 16P
   2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM
logo
List of Unclassifed Man...
AM24LC02 ETC-AM24LC02 Datasheet
171Kb / 12P
   2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM
logo
Anachip Corp
AM24LC16 ANACHIP-AM24LC16 Datasheet
203Kb / 10P
   2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM
logo
Samsung semiconductor
KM28C64A SAMSUNG-KM28C64A Datasheet
364Kb / 12P
   8K x 8 BIT CMOS ELECTRICALLY ERASABLE PROM
logo
List of Unclassifed Man...
TU24C04 ETC2-TU24C04 Datasheet
39Kb / 8P
   CMOS I2C 2-WIRE BUS 4K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 512 X 8 BIT EEPROM
24C04 ETC1-24C04 Datasheet
44Kb / 8P
   CMOS I2C 2-WIRE BUS 4K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 512 X 8 BIT EEPROM
logo
Integrated Silicon Solu...
IS25C02 ISSI-IS25C02 Datasheet
134Kb / 17P
   2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM
IS93C46A ISSI-IS93C46A Datasheet
74Kb / 13P
   1,024-BIT SERIAL ELECTRICALLY ERASABLE PROM
logo
Rohm
BR93LC46 ROHM-BR93LC46 Datasheet
133Kb / 12P
   1,024-Bit Serial Electrically Erasable PROM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com