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IDT72V7280L Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT72V7280L Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 42 page 4 COMMERCIALTEMPERATURERANGE IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO 512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72 BM IW OW Write Port Width Read Port Width L X X x72 x72 H H L x36 x72 H H H x18 x72 H L L x72 x36 H L H x72 x18 TABLE 1 — BUS-MATCHING CONFIGURATION MODES During Master Reset ( MRS)thefollowingeventsoccur: thereadandwrite pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset ( PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore PartialResetremainunchanged. Theflagsareupdatedaccordingtothetiming modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation, when reprogramming programmable flags would be undesirable. Itisalsopossibletoselectthetimingmodeofthe PAE(ProgrammableAlmost- Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE and PAFflags. If asynchronous PAE/PAF configuration is selected, the PAEis asserted LOWontheLOW-to-HIGHtransitionofRCLK. PAEisresettoHIGHontheLOW- to-HIGH transition of WCLK. Similarly, the PAFisassertedLOWontheLOW- to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Ifsynchronous PAE/PAFconfigurationisselected,thePAEisassertedand updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The modedesiredisconfiguredduringmasterresetbythestateoftheProgrammable Flag Mode (PFM) pin. The Retransmit function allows data to be reread from the FIFO more than once. A LOW on the RTinputduringarisingRCLKedgeinitiatesaretransmit operation by setting the read pointer to the first location of the memory array. A zero-latency retransmit timing mode can be selected using the Retransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select zero latency retransmit. A HIGH on RM during Master Reset will select normal latency. If zero latency retransmit operation is selected, the first data word to be retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK edge that initiated the retransmit based on RT being LOW. Refer to Figure 16 and 17 for Retransmit Timingwith normal latency. Refer to Figure 18 and 19 for Zero Latency Retransmit Timing. The device can be configured with different input and output bus widths as shown in Table 1. A Big-Endian/Little-Endian data word format is provided. This function is useful when the FIFO is used in Bus-Matching mode, to determine order of the words. Asanexample,ifBig-Endianmodeisselected,thenthemostsignificant word of the long word written into the FIFO will be read out of the FIFO first, followedbytheleastsignificantword. IfLittle-Endianformatisselected,thenthe least significant word of the long word written into the FIFO will be read out first, followed by the most significant word. The mode desired is configured during master reset by the state of the Big-Endian ( BE) pin. The Interspersed/Non-Interspersed Parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFOwillassumethattheparitybitislocatedinbitpositionD8duringtheparallel programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during Master Reset by the state of the IP input pin. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. Both an Asynchronous Output Enable pin ( OE) and Synchronous Read Chip Select pin ( RCS) are provided on the FIFO. The Synchronous Read ChipSelect issynchronizedtotheRCLK. Boththeoutputenableandreadchip selectcontroltheoutputbufferoftheFIFO,causingthebuffertobeeitherHIGH impedance or LOW impedance. JTAG test pins are also provided, the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/ 72V7290/72V72100 are fabricated using IDT’s high speed submicron CMOS technology. |
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