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IDT72V7240L10 Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT72V7240L10 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 42 page  1 DECEMBER 2003 DSC-4680/9 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. 3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO 512 x 72, 1,024 x 72 2,048 x 72, 4,096 x 72 8,192 x 72, 16,384 x 72 32,768 x 72, 65,536 x 72 IDT72V7230, IDT72V7240 IDT72V7250, IDT72V7260 IDT72V7270, IDT72V7280 IDT72V7290, IDT72V72100 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE FEATURES: ••••• Choose among the following memory organizations: IDT72V7230 512 x 72 IDT72V7240 1,024 x 72 IDT72V7250 2,048 x 72 IDT72V7260 4,096 x 72 IDT72V7270 8,192 x 72 IDT72V7280 16,384 x 72 IDT72V7290 32,768 x 72 IDT72V72100 65,536 x 72 ••••• 100 MHz operation (10 ns read/write cycle time) ••••• User selectable input and output port bus-sizing - x72 in to x72 out - x72 in to x36 out - x72 in to x18 out - x36 in to x72 out - x18 in to x72 out ••••• Big-Endian/Little-Endian user selectable word representation ••••• Fixed, low first word latency ••••• Zero latency retransmit ••••• Auto power down minimizes standby power consumption ••••• Master Reset clears entire FIFO ••••• Partial Reset clears data, but retains programmable settings ••••• Empty, Full and Half-Full flags signal FIFO status ••••• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets ••••• Selectable synchronous/asynchronous timing modes for Almost- Empty and Almost-Full flags ••••• Program programmable flags by either serial or parallel means ••••• Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) ••••• Output enable puts data outputs into high impedance state ••••• Easily expandable in depth and width ••••• Independent Read and Write Clocks (permit reading and writing simultaneously) ••••• Asynchronous operation of Output Enable, OE ••••• Read Chip Select ( RCS ) on Read Side ••••• Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA) ••••• Features JTAG (Boundary Scan) ••••• High-performance submicron CMOS technology ••••• Industrial temperature range (–40 °°°°°C to +85°°°°°C) is available FUNCTIONAL BLOCK DIAGRAM INPUT REGISTER OUTPUT REGISTER RAM ARRAY 512 x 72 1,024 x 72 2,048 x 72 4,096 x 72 8,192 x 72 16,384 x 72 32,768 x 72 65,536 x 72 FLAG LOGIC FF/IR PAF EF/OR PAE HF READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC RESET LOGIC WEN WCLK D0 -Dn (x72, x36 or x18) LD MRS REN RCLK Q0 -Qn (x72, x36 or x18) OFFSET REGISTER FWFT/SI SEN RT 4680 drw01 BUS CONFIGURATION BM CONTROL LOGIC BE OW IP PFM FSEL0 FSEL1 IW RM SCLK OE PRS JTAG CONTROL (BOUNDARY SCAN) TCK TMS TRST TDO TDI RCS WRITE POINTER |
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