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IDT72V7240L15BB Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT72V7240L15BB Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 42 page  8 COMMERCIALTEMPERATURERANGE IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO 512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72 AC ELECTRICAL CHARACTERISTICS(1) (Commercial: VCC = 3.3V ± 0.15V, TA = 0 °C to +70°C; JEDEC JESD8-A compliant) Commercial IDT72V7230L10 IDT72V7230L15 IDT72V7240L10 IDT72V7240L15 IDT72V7250L10 IDT72V7250L15 IDT72V7260L10 IDT72V7260L15 IDT72V7270L10 IDT72V7270L15 IDT72V7280L10 IDT72V7280L15 IDT72V7290L10 IDT72V7290L15 IDT72V72100L10 IDT72V72100L15 Symbol Parameter Min. Max. Min. Max. Unit fS Clock Cycle Frequency — 100 — 66.7 MHz tA Data Access Time 1 6.5 1 10 ns tCLK Clock Cycle Time 10 — 15 — ns tCLKH Clock High Time 4.5 — 6 — ns tCLKL Clock Low Time 4.5 — 6 — ns tDS DataSetupTime 3.5 — 4 — ns tDH Data Hold Time 0.5 — 1 — ns tENS Enable Setup Time 3.5 — 4 — ns tENH Enable Hold Time 0.5 — 1 — ns tLDS LoadSetupTime 3.5 — 4 — ns tLDH Load Hold Time 0.5 — 1 — ns tRS Reset Pulse Width(2) 10 — 15 — ns tRSS ResetSetupTime 10 — 15 — ns tRSR Reset Recovery Time 10 — 15 — ns tRSF Reset to Flag and Output Time — 15 — 15 ns tFWFT Mode Select Time 0 — 0 — ns tRTS RetransmitSetupTime 3.5 — 4 — ns tOLZ Output Enable to Output in Low Z (3) 1— 1 — ns tOE Output Enable to Output Valid 1 6 1 8 ns tOHZ Output Enable to Output in High Z (3) 16 1 8 ns tWFF Write Clock to FF or IR — 6.5 — 10 ns tREF Read Clock to EF or OR — 6.5 — 10 ns tPAFA Clock to Asynchronous Programmable Almost-Full Flag — 16 — 20 ns tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 6.5 — 10 ns tPAEA Clock to Asynchronous Programmable Almost-Empty Flag — 16 — 20 ns tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 6.5 — 10 ns tHF Clock to HF —16 — 20 ns tRCSS RCS Setup Time 3.5 — 5 — ns tRCSH RCS Hold Time 0.5 — 1 — ns tRCSLZ RCLK to Active from High-Z(3) 1 6.5 1 10 ns tRCSHZ RCLK to High-Z(3) 1 6.5 1 10 ns tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 7— 9 — ns tSKEW2 Skew time between RCLK and WCLK for PAE and PAF 10 — 14 — ns NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. 4. Data Sheet slow conditions: 85 °c, 3.0V. Data Sheet fast conditions: -40°c, 3.6V. Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V OutputReferenceLevels 1.5V OutputLoad See Figure 2 AC TEST CONDITIONS Figure 2. Output Load * Includes jig and scope capacitances 4680 drw04 330 Ω 30pF* 510 Ω 3.3V D.U.T. |
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