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LTC2625IGN Datasheet(PDF) 9 Page - Linear Technology |
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LTC2625IGN Datasheet(HTML) 9 Page - Linear Technology |
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9 / 16 page  9 LTC2605/LTC2615/LTC2625 2605f BLOCK DIAGRA TI I G DIAGRA Figure 1 2 15 1 GND VOUT A VOUT B VOUT C VOUT D REF CA2 SCL VCC VOUT H VOUT G VOUT F VOUT E CA0 CA1 SDA 2605/15/25 BD01 16 DAC A 3 14 4 13 5 7 6 8 10 11 9 12 2-WIRE INTERFACE 32-BIT SHIFT REGISTER DAC H DAC B DAC G DAC C DAC F DAC D DAC E SDA tf S tr tLOW tHD(STA) ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS tHD(DAT) tSU(DAT) tSU(STA) tHD(STA) tSU(STO) tSP tBUF tr tf tHIGH SCL S P S 2605/15/25 TD01 PIN FUNCTIONS GND (Pin 1): Analog Ground. VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Voltage Output. The output range is 0V to VREF. REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC. CA2 (Pin 7): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 2). SCL (Pin 8): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This is a high impedance pin while data is shifted in. It is an open- drain N-channel output during acknowledgment. This pin requires a pull-up resistor or current source to VCC. CA1 (Pin 10): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 2). CA0 (Pin 11): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 2). VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V. |
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