HY62UF08401C Series

Rev.02 / Jun.01

7

Notes:

1. A write occurs during the overlap of a low /WE and a low /CS.

2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the

output must not be applied.

4. If the /CS low transition occurs simultaneously with the /WE low transition or after the

/WE transition, outputs remain in a high impedance state.

5. Q(data out) is the same phase with the write data of this write cycle.

6. Q(data out) is the read data of the next address.

7. Transition is measured + 200mV from steady state.

This parameter is sampled and not 100% tested.

8. /CS in high for the standby, low for active

DATA RETENTION ELECTRIC CHARACTERISTIC

°C to 85°C

Symbol

Parameter

Test Condition

Min

Typ

1.

Max

Unit

Vcc for Data Retention

/CS > Vcc - 0.2V,

1.2

-

3.3

V

SL

-

0.1

3

uA

Iccdr

Data Retention Current

Vcc=1.5V,

/CS > Vcc - 0.2V or

LL

-

0.1

10

uA

tCDR

Chip Deselect to Data

Retention Time

0

-

-

ns

tR

Operating Recovery Time

See Data Retention Timing Diagram

tRC

-

-

ns

Notes:

°C.

2. Typical value are sampled and not 100% tested

DATA RETENTION TIMING DIAGRAM

/CS

VDR

/CS >VCC-0.2V

tCDR

tR

VSS

VCC

2.7V

VIH

DATA RETENTION MODE