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IDT71V547S80PFI Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT71V547S80PFI Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 19 page 10 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT ™ ™ ™ ™ ™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. 3. Device outputs are ensured to be in High-Z during device power-up. Read Operation with Chip Enable Used(1) NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Write Operation with Chip Enable Used(1) Cycle Address R/W ADV/LD CE (1) CEN BW x OE I/O(3) Comments n X X L H L X X ? Deselected n+1 X X L H L X X Z Deselected n+2 A0 H L L L X X Z Address A0 and Control meet setup n+3 X X L H L X L Q0 Address A0 read out. Deselected n+4 A1 H L L L X X Z Address A1 and Control meet setup n+5 X X L H L X L Q1 Address A1 Read out. Deselected n+6 X X L H L X X Z Deselected n+7 A2 H L L L X X Z Address A2 and Control meet setup n+8 X X L H L X L Q2 Address A2 read out. Deselected n+9 X X L H L X X Z Deselected 3822 tbl 18 C ycle Address R/W AD V/LD CE (1 ) CEN BW x OE I/O C omments n X X L H L X X ? D eselected n+ 1 X X L H L X X Z D eselected n+ 2 A0 L L L L L X Z Address A 0 and C ontrol m eet setup n+ 3 X X L H L X X D0 Addres s D 0 W rite In. D eselected n+ 4 A1 L L L L L X Z Address A 1 and C ontrol m eet setup n+ 5 X X L H L X X D1 Addres s D 1 W rite In. D eselected n+ 6 X X L H L X X Z D eselected n+ 7 A2 L L L L L X Z Address A 2 and C ontrol m eet setup n+ 8 X X L H L X X D2 Addres s D 2 W rite In. D eselected n+ 9 X X L H L X X Z D eselected 3822 tbl 19 |
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