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MAX4723 Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX4723 Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 14 page Power-Supply Bypassing Power-supply bypassing improves noise margin and prevents switching noise from propagating from the V+ supply to other components. A 0.1µF capacitor connect- ed from V+ to GND is adequate for most applications. Power-Supply Sequencing and Overvoltage Protection Caution: Do not exceed the absolute maximum rat- ings because stresses beyond the listed ratings may cause permanent damage to the device. UCSP Package Considerations For general UCSP package information and PC layout considerations, please refer to the Maxim Application Note (Wafer-Level Chip-Scale Package). UCSP Reliability The chip-scale package (UCSP) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical relia- bility tests. UCSP reliability is integrally linked to the user’s assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a UCSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. Mechanical stress performance is a greater considera- tion for a UCSP package. UCSPs are attached through direct solder contact to the user’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be consid- ered. Information on Maxim’s qualification plan, test data, and recommendations are detailed in the UCSP application note, which can be found on Maxim’s web- site at www.maxim-ic.com. 4.5 Ω Dual SPST Analog Switches in UCSP _______________________________________________________________________________________ 9 Test Circuits/Timing Diagrams 50% VIL LOGIC INPUT RL COM_ GND IN_ CL INCLUDES FIXTURE AND STRAY CAPACITANCE. VOUT = VCOM VN_ VIH tOFF 0V NO_ OR NC_ 0.9 x V0UT 0.9 x VOUT tON VOUT SWITCH OUTPUT LOGIC INPUT LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. V+ CL V+ VOUT MAX4721/ MAX4722/ MAX4723 ( RL RL - RON ) Figure 1. Switching Time LOGIC INPUT RL2 GND CL INCLUDES FIXTURE AND STRAY CAPACITANCE. NO_ IN_ NC_ VOUT2 V+ V+ CL2 MAX4723 RL1 CL1 VOUT1 VCOM1 VCOM2 50% 0.9 x V0UT1 VIH VIL 0V LOGIC INPUT SWITCH OUTPUT 2 (VOUT2) 0V 0.9 x VOUT2 tD tD SWITCH OUTPUT 1 (VOUT1) COM2 COM1 Figure 2. Break-Before-Make Interval |
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