MK2049-45SI datasheet(1/9 Pages) ICST

Part #	MK2049-45SI

Description	3.3V Communications Clock PLL

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MK2049-45

MDS 2049-45 G

1

Revision 101904

Integrated Circuit Systems, Inc.

● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

3.3V Communications Clock PLL

Description

The MK2049-45 is a dual Phase-Locked Loop (PLL)

device which can provide frequency synthesis and jitter

attenuation. The first PLL is VCXO based and uses a

pullable crystal to track signal wander and attenuate

input jitter. The second PLL is a translator for frequency

multiplication. Basic configuration is determined by a

Mode/Frequency Selection Table. Loop bandwidth and

damping factor are programmable via external loop

filter component selection.

Buffer Mode accepts a 10 to 50MHz input and will

provide a jitter attenuated output at 0.5 x ICLK, 1 x

ICLK or 2 x ICLK. In this mode the MK2049-45 is ideal

for filtering jitter from high frequency clocks.

In External Mode, ICLK accepts an 8 kHz clock and will

produce output frequencies from a table of common

communciations clock rates, CLK and CLK/2. This

allows for the generation of clocks frequency-locked to

an 8 kHz backplane clock, simplifying clock

synchronization in communications systems.

The MK2049-45 can be dynamically switched between

T1, E1, T3, E3 outputs with the same 24.576 MHz

crystal.

ICS can customize these devices for many other

different frequencies. Contact your ICS representative

for more details.

Features

• Packaged in 20 pin SOIC

• 3.3 V + 5% operation

• Meets the TR62411, ETS300 011, and GR-1244

specification for MTIE, Pull-in/Hold-in Range, Phase

Transients, and Jitter Generation for Stratum 3, 4,

and 4E

• Accepts multiple inputs: 8 kHz backplane clock, or 10

to 50 MHz

• Locks to 8 kHz + 100 ppm (External mode)

• Buffer Mode allows jitter attenuation of 10 - 50 MHz

input and x1 / x0.5 or x1 / x2 outputs

• Exact internal ratios enable zero ppm error

• Output rates include T1, E1, T3, E3, and OC3

submultiples

• Available in Pb (lead) free package

• See also the MK2049-34 and MK2049-36

Block Diagram

Charge

Pump

VCXO

X2

X1

ISET

CAP2

Feedback

Divider (N)

Reference

Divider

(used in buffer

mode only)

ICLK

Reference

Divider

Phase

Detector

VCXO

PLL

Feedback

Divider

VCO

Translator

PLL

CLK

CAP1

Output

Divider

Divide

by 2

CLK/2

8k

R

S

R

SET

C

P

C

S

Optional Crystal Load Caps

Divider Value

Look-up Table

FS3:0

4

C

L

C

L

External Pullable Crystal

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