3.3V Communications Clock PLL

MDS 2049-45 G

2

Revision 101904

Integrated Circuit Systems, Inc.

MK2049-45

Pin Assignment

Pin Descriptions

16

1

15

2

14

FS1

FS0

3

13

X2

4

12

X1

RES

5

11

VDD

6

CAP2

7

FCAP

8

VDD

GND

CAP1

VDD

GND

GND

CLK

ICLK

9

10

CLK/2

FS3

8k

FS2

20

19

18

17

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

FS1

Input

Frequency select 1. Determines CLK input/outputs per table on page 2.

Internal pull-up resistor.

2

X2

Input

Crystal connection. Connect to a MHz crystal as shown in table on page 2.

3

X1

Input

Crystal connection. Connect to a MHz crystal as shown in table on page 2.

4

VDD

Power

Power supply. Connect to +3.3V.

5

FCAP

-

Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.

6

VDD

Power

Power supply. Connect to +3.3V.

7

GND

Power

Connect to ground

8

CLK

Output

Clock output determined by status of FS3:0 per tables on page 2.

9

CLK/2

Output

Clock output determined by status of FS3:0 per tables page 2. Always 1/2 of

CLK.

10

8k

Output

Recovered 8 kHz clock output.

11

FS2

Input

Frequency select 2. Determines CLK input/outputs per table on page 2.

Internal pull-up resistor.

12

FS3

Input

Frequency select 3. Determines CLK input/outputs per table on page 2.

Internal pull-up resistor.

13

ICLK

Input

Input clock connection. Connect to 8 kHz backplane or MHz clock.

14

GND

Power

Connect to ground.

15

VDD

Power

Power Supply. Connect to +3.3V.

16

CAP1

Loop

Filter

Connect the loop filter capacitors and resistor between this pin and CAP2.

17

GND

Power

Connect to ground.