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MK2049-45SILF Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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MK2049-45SILF Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 9 page 3.3V Communications Clock PLL MDS 2049-45 G 5 Revision 101904 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK2049-45 Charge Pump Current Table Special considerations must be made in choosing loop components CS and CP. These recommendations can be found at http://www.icst.com/products/telecom/loopfiltercap.htm Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50 Ω trace (a commonly used trace impedance), place a 33 Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 Ω. (The optional series termination resistor is not shown in the External Component Schematic.) Decoupling Capacitors As with any high performance mixed-signal IC, the MK2049-45 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the MK2049-45 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. Recommended Power Supply Connection for Optimal Device Performance Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground, shown as CL in the External Component Schematic. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Please refer to MAN05 for the procedure to determine capacitor values. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please also refer to the Recommended PCB Layout drawing on Page 7. 1) Each 0.01 µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The loop filter components must also be placed close to the CHGP and VIN pins. CP should be closest to the device. Coupling of noise from other system RSET (k Ω) Charge Pump Current (ICP) (µA) 13.02 139 15 125 16 119 18 109 20 100 22 93 24 86 27 68 36 56 47 43 56 35 75 28 100 22 150 15 200 12 Connection to 3.3V Power Plane Ferrite Bead Bulk Decoupling Capacitor (such as 1 µF Tantalum) VDD Pin VDD Pin VDD Pin 0.01 µF Decoupling Capacitors |
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