2
REV.1.8, JUL. 13 , 1998
P/N: PM0455
Patent#: US#5,523,307
MX26C512A
FUNCTIONAL DESCRIPTION
When the MX26C512A is delivered, or it is erased, the
chip has all 512K bits in the "ONE", or HIGH state.
"ZEROs" are loaded into the MX26C512 through the
procedure of programming.
PROGRAMMING MODE
PROGRAMMMING ALGORITHM
The MX26C512A is programmed by an EPROM
programmer or on-board. The device is set up in the
programming mode when the programming voltage OE/
VPP = 12.75V is applied, with VCC = 5 V (Algorithm
shown in Figure 1). Programming is achieved by applying
a single TTL low level 25us pulse to the CE input after
addresses and data lines are stable. If the data is not
verified, additional pulses are applied for a maximum of
20 pulses. After the data is verified, one 25us pulse is
applied to overprogram the byte so that program margin
is assured. This process is repeated while sequencing
through each address of the device. When programming
is completed, the data at all the addresses are verified
at VCC = 5V ± 10%.
The VCC supply of the MXIC On-Board Programming
Algorithm is designed to be 5V ± 10% particularly to
facilitate the programming operation under the on-board
application environment. But it can also be implemented
in an industrial-standard EPROM programmer.
COMPATIBILITY WITH MX27C512 FAST PROGRAMMING
ALGORITHM
Besides the On-Board Programming Algorithm, the Fast
Programming Algorithm of MX27C512 also applies to
MX26C512A. MXIC Fast Algorithm is the conventional
EPROM programing algorithm and is available in
industrial-standard EPROM programmers.
A user of
industrial-standard EPROM programmer can choose
either of the algorithms base on his preference.
The device is set up in the fast programming mode when
the programming voltage OE/VPP = 12.75V isapplied,
with VCC = 6.25V, (Algorithm is shown in Figure 2). The
programming is achieved by appling a single TTL low
level 25~100us pulse to the CE input after addresses and
data line are stable. If the data is not verified, an additional
pulse is applied for a maximum of 25 pulses. This process
is repeated while sequencing through each address of
the device. When the programming mode is completed,
the data in all address is verified at VCC = 5V ± 10%.
ERASE MODE
The MX26C512A is erased by EPROM programmer or
in-system. The device is set up in erase mode when
A9 =OE/VPP = 12.75V are applied, with VCC = 5V.
(Algorithm is shown in Figure 3). The erase time is around
1sec. If the erase is not verified, an additional erase
processes will be repeated for a maximum of 200 times.
PROGRAM INHIBIT MODE
Programming of multiple MX26C512A in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX26C512 may be common. A
TTL low-level program pulse applied to an MX26C512A
CE input with OE/VPP = 12.75 ± 0.25 V will program
that MX26C512A. A high-level CE input inhibits the other
MX26C512A from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits
to determine that they were correctly programmed. The
verification should be performed with OE/VPP and CE,
at VIL. Data should be verified tDV after the falling edge
of CE.
ERASE VERIFY MODE
Verification should be performed on the erased chip to
determine that whole chip(all bits) was correctly erased.
Verification should be performed with OE/VPP and CE
at VIL and VCC = 5V.
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from a MTP that will identify its manufacturer and
device type.
This mode is intended for use by
programming equipment for the purpose of automatically
matching the device to be programmed with its
corresponding programming algorithm.
This mode is
functional in the 25°C ± 5°C ambient temperature range
that is required when programming the MX26C512A.
To activate this mode, the programming equipment must
force 12.75V on address line A9 of the device. Two
identifier bytes may then be sequenced from the device
outputs by toggling address line A0 from VIL to VIH. All
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