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S93WD663S-B Datasheet(PDF) 2 Page - Summit Microelectronics, Inc. |
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S93WD663S-B Datasheet(HTML) 2 Page - Summit Microelectronics, Inc. |
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2 / 14 page  2 S93WD662/S93WD663 2013 2.1 8/2/00 PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC +2.7 to 6.0V Power Supply GND Ground RESET/RESET# RESET I/O PIN CONFIGURATION DEVICE OPERATION APPLICATIONS The S93WD662/WD663 is ideal for applications requir- ing low voltage and low power consumption. This device provides microcontroller RESET control and can be manually resettable. RESET CONTROLLER DESCRIPTION The S93WD662/WD663 provides a precision reset con- troller that ensures correct system operation during brownout and power-up/-down conditions. It is config- ured with two open drain reset outputs: pin 7 is an active high output and pin 6 is an active low output. During power-up, the reset outputs remain active until VCC reaches the VTRIP threshold. The outputs will con- tinue to be driven for approximately 200ms after reach- ing VTRIP. The reset outputs will be valid so long as VCC is ≥ 1.0V. During power-down, the reset outputs will begin driving active when VCC falls below VTRIP. The reset pins are I/Os; therefore, the S93WD662/ WD663 can act as a stabilization circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset time-out after detecting a low to high transition and the RESET# input will initiate a reset time-out after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a debounce/reset ex- tender circuit. It should be noted the reset outputs are open drain. When used as outputs driving a circuit they need to be either tied high (RESET#) or tied to ground (RESET) through the use of pull-up or pull-down resistors. Refer to the applications aid section for help in determining the value of resistor to be used. Internally these pins are weakly pulled up (RESET#) and pulled down (RESET). If the signals are not being used the pins may be left unconnected. WATCHDOG TIMER DESCRIPTION The S93WD662/WD663 has a watchdog timer with a nominal time-out period of 1.6 seconds. Whenever the watchdog times out, it will generate a reset output to both pins 6 and 7. The watchdog timer is reset by any transition on CS. The watchdog timer will be held in a reset state during power-on while VCC is less than VTRIP. Once VCC ex- ceeds VTRIP the watchdog will continue to be held in a reset state for the tPURST period. After tPURST it will be released and the timer will begin operation. If either reset input is asserted the watchdog timer will be reset and remain in the reset condition until either tPURST has expired or the reset input is released, whichever is longer. GENERAL OPERATION The S93WD662/WD663 is a 4096-bit nonvolatile memory intended for use with industry standard microproces- sors. The S93WD663 is organized as X16, seven 11-bit instructions control the reading, writing and erase op- erations of the device. The S93WD662 is organized as X8, seven 12-bit instructions control the reading, writing and erase operations of the device. The device operates on a single 3V or 5V supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. CS SK DI DO VCC RESET RESET# GND 1 2 3 4 8 7 6 5 8-Pin SOIC 2014 T PCon 2.0 |
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