MSM5265

¡ Semiconductor

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FUNCTIONAL DESCRIPTION

Operational Description

The MSM5265 consists of a 160-stage shift register, 160-bit data latch, and 80 pairs of LCD

drivers. The display data is input from the DATA-IN pin to the 160-stage shift register at the

rising edge of the CLOCK pulse and it is shifted to the 160-bit data latch when the LOAD

signal is set at "H" level, then it is directly output from the 80 pairs of LCD drivers to the LCD

panel. Input the display data in the order of SEG80, SEG79, SEG78, ..., SEG2, SEG1.

DATA LATCH

Output

(inside the IC)

1

23456

159

160

DATA-IN

CLOCK

LOAD

Pin Functional Description

• OSC-IN, OSC-OUT, OSC-OUT

generate the common signal is formed.

This frequency is divided into either 1/8 or 1/4 by the internal dividing circuit. The 1/8

divided frequency is used in the static display mode, while the 1/4 divided frequency is used

as the common signal in the 1/2 duty dynamic display mode which is output from the COM-

OUT pin. (EXT/INT should be set at low level.)

When the external common signal is used, the EXT/INT pin should be set at high level and

the external common signal should be input from the OSC-IN pin.

=

OSC-OUT

OSC-OUT

(MSM5265)

OSC-IN