HY57V283220TP-6 datasheet(8/15 Pages) HYNIX

Part #	HY57V283220TP-6

Description	4 Banks x 1M x 32Bit Synchronous DRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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8 / 15 page

Rev. 0.9 / July 2004

8

HY57V283220(L)T(P) / HY5V22(L)F(P)

DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)

Note :

1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3.HY57V283220T(P)(HY5V22F(P))-5/55/6/7/H/8/P/S

4.HY57V283220LT(P)(HY5V22LF(P))-5/55/6/7/H/8/P/S

Parameter

Symbol

Test Condition

Speed

Unit

Note

-5

-55

-6

-7

-H

-8

-P

S

Operating Current

IDD1

Burst length=1, One bank active

tRC

≥ tRC(min), IOL=0mA

120

110

100

90

mA

1

Precharge Standby Current

in power down mode

IDD2P

CKE

≤ VIL(max), tCK = 10ns

2

mA

IDD2PS

CKE

≤ VIL(max), tCK =

∞

1

Precharge Standby Current

in non power down mode

IDD2N

CKE

≥ VIH(min), CS ≥ VIH(min),

tCK = 10ns Input signals are changed one

time during 2clks. All other pins

≥ VDD-

0.2V or

≤ 0.2V

14

mA

IDD2NS

CKE

≥ VIH(min), tCK =

∞

Input signals are stable.

9

Active Standby Current

in power down mode

IDD3P

CKE

≤ VIL(max), tCK = 10ns

7

mA

IDD3PS

CKE

≤ VIL(max), tCK =

∞

6

Active Standby Current

in non power down mode

IDD3N

CKE

≥ VIH(min), CS ≥ VIH(min),

tCK = 10ns

Input signals are changed

one time during 2clks. All other pins

≥ VDD-0.2V or ≤ 0.2V

17

mA

IDD3NS

CKE

≥ VIH(min), tCK =

∞

Input signals are stable.

13

Burst Mode Operating

Current

IDD4

t

tCK

≥ tCK(min),

IOL=0mA

All banks active

CL=3

230

220

200

180

150

130

mA

1

CL=2

-

---

--

130

Auto Refresh Current

IDD5

tRC

≥ tRC(min), All banks active

170

160

150

140

mA

2

Self Refresh Current

IDD6

CKE

≤ 0.2V

2

mA

3

0.8

4

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