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M374S6453CTS-L7C Datasheet(PDF) 10 Page - Samsung semiconductor

Part # M374S6453CTS-L7C
Description  M374S6453CTS PC133/PC100 Unbuffered SDRAM DIMM
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

M374S6453CTS-L7C Datasheet(HTML) 10 Page - Samsung semiconductor

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PC133/PC100 Unbuffered DIMM
M374S6453CTS
REV. 0.1 Sept. 2001
Byte#.
Function described
Function Supported
Hex value
Note
-7C
-7A
-1H
-1L
-7C
-7A
-1H
-1L
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
13
0Dh
1
4
# of column address on this assembly
10
0Ah
1
5
# of module Rows on this assembly
2 Row
02h
6
Data width of this assembly
72 bits
48h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time from clock @CAS latency of 3
7.5ns
7.5ns
10ns
10ns
75h
75h
A0h
A0h
2
10
SDRAM access time from clock @CAS latency of 3
5.4ns
5.4ns
6ns
6ns
54h
54h
60h
60h
2
11
DIMM configuration type
ECC
02h
12
Refresh rate & type
7.8us, support self refresh self
82h
13
Primary SDRAM width
x8
08h
14
Error checking SDRAM width
x8
08h
15
Minimum clock delay for back-to-back random column
tCCD = 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of banks on SDRAM device
4 banks
04h
18
SDRAM device attributes : CAS latency
2 & 3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Non-buffered/Non-Registered &
redundant addressing
00h
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
7.5ns
10ns
10ns
12ns
75h
A0h
A0h
C0h
2
24
SDRAM access time @CAS latency of 2
5.4ns
6ns
6ns
7ns
54h
60h
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
00h
2
26
SDRAM access time @CAS latency of 1
-
00h
2
27
Minimum row precharge time (=tRP)
15ns
20ns
20ns
20ns
0Fh
14h
14h
14h
28
Minimum row active to row active delay (tRRD)
15ns
15ns
20ns
20ns
0Fh
0Fh
14h
14h
29
Minimum RAS to CAS delay (=tRCD)
15ns
20ns
20ns
20ns
0Fh
14h
14h
14h
30
Minimum activate precharge time (=tRAS)
45ns
45ns
50ns
50ns
2Dh
2Dh
32h
32h
31
Module Row density
2 Row of 256MB
40h
32
Command and Address signal input setup time
1.5ns
1.5ns
2ns
2ns
15h
15h
20h
20h
33
Command and Address signal input hold time
0.8ns
0.8ns
1ns
1ns
08h
08h
10h
10h
34
Data signal input setup time
1.5ns
1.5ns
2ns
2ns
15h
15h
20h
20h
M374S6453CTS-L7C/L7A/L1H/L1L, C7C/C7A/C1H/C1L
• Organization : 64MX64
• Composition : 32MX8 *18
• Used component part # : K4S560832C-TL7C/7A/1H/1L,TC7C/7A/1H/1L
• # of rows in module : 2row
• # of banks in component : 4 banks
• Feature : 1,375 mil height & double sided component
• Refresh : 8K/64ms
• Contents :


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