 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AX88178 Datasheet(PDF) 5 Page - ASIX Electronics Corporation |
|
||||||||||||||||||||||||||||||
AX88178 Datasheet(HTML) 5 Page - ASIX Electronics Corporation |
|
|
5 / 35 page  ASIX ELECTRONICS CORPORATION 5 AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 2.0 Signal Description The following abbreviations apply to the following pin description table. I2 Input, 2.5V with 3.3V tolerant B2 Bi-directional I/O, 2.5V with 3.3V tolerant I3 Input, 3.3V B5 Bi-directional I/O, 3.3V with 5V tolerant I5 Input, 3.3V with 5V tolerant PU Internal Pull Up (75K) O2 Output, 2.5V with 3.3V tolerant PD Internal Pull Down (75K) O3 Output, 3.3V P Power Pin O5 Output, 3.3V with 5V tolerant S Schmitt Trigger B Bi-directional I/O Table 1: Pinout Descripton Pin Name Type Pin No Pin Description USB Interface DP B 32 USB 2.0 data positive pin. DM B 31 USB 2.0 data negative pin. DPRS B 36 USB 1.1 data positive pin. Please connect to DP through a 39ohm (+/-1%) serial resistor. DMRS B 35 USB 1.1 data negative pin. Please connect to DM through a 39ohm (+/-1%) serial resistor. VBUS I5/PD/S 10 VBUS pin input. Please connect to USB bus power. XIN12M I3 26 12Mhz crystal or oscillator clock input. This clock is needed for USB PHY transceiver to operate. XOUT12M O3 27 12Mhz crystal or oscillator clock output. RREF I 30 For USB PHY’s internal biasing. Please connect to AGND through a 12.1Kohm (+/-1%) resistor. RPU I 34 For USB PHY’s internal biasing. Please connect to AVDD3 (3.3V) through a 1.5Kohm (+/-5%) resistor. Station Management Interface MDC O2 121 Station Management Data Clock output. The timing reference for MDIO. All data transfers on MDIO are synchronized to the rising edge of this clock. The frequency of MDC is 1.5MHz. MDIO B2/PU 120 Station Management Data Input/Output. Serial data input/output transfers from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII spec. MDINT I2/PU 117 Station Management Interrupt input. MII/GMII/RGMII Interface RX_CLK I2 104 Receive Clock. RX_CLK is received from PHY to provide timing reference for the transfer of RXD [7:0], RX_DV, and RX_ER signals on receive direction of MII/GMII/RGMII interface. RXD [7:0] I2 114, 113, 112, 111, 110, 109, 108, 107 Receive Data. RXD [7:0] is driven synchronously with respect to RX_CLK by PHY. In RGMII mode, only RXD [3:0] is used. RX_DV I2 105 Receive Data Valid. RX_DV is driven synchronously with respect to RX_CLK by PHY. It is asserted high when valid data is present on RXD [7:0]. In RGMII mode, RX_DV acts as RX_CTL. RX_ER I2 106 Receive Error. RX_ER is driven synchronously with respect to RX_CLK by PHY. It is asserted high for one or more RX_CLK periods to indicate to the MAC that an error has detected. COL I2 116 Collision Detected. COL is driven high by PHY when the collision is detected. CRS I2 115 Carrier Sense. CRS is asserted high asynchronously by the PHY when either transmit or receive medium is non-idle. |
Similar Part No. - AX88178 |
|
Similar Description - AX88178 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
