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ISPLSI2064V-100LJ44 Datasheet(PDF) 10 Page - Lattice Semiconductor |
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ISPLSI2064V-100LJ44 Datasheet(HTML) 10 Page - Lattice Semiconductor |
10 / 14 page 10 Specifications ispLSI 2064V Pin Description Input/Output Pins — These are the general purpose I/O pins used by the logic array. NAME Table 2-0002B/2064V 44-PIN PLCC PIN NUMBERS DESCRIPTION 15, 19, 25, 29, 37, 41, 3, 7, 2 11 35 13 14 36 24 33 1, 12, 16, 20, 26, 30, 38, 42, 4, 8, 23 34 17, 21, 27, 31, 39, 43, 5, 9, I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 GOE 0/IN 3 GOE 1/Y0 RESET/Y1 ispEN TDI/IN 0 TMS/IN 2 TDO/IN 1 TCK/Y2 GND VCC 18, 22, 28, 32, 40, 44, 6, 10 44-PIN TQFP PIN NUMBERS 9, 13, 19, 23, 31, 35, 41, 1, 40 5 29 7 8 30 18 27 17, 6, 10, 14, 20, 24, 32, 36, 42, 2, 39 28 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4 This pin performs one of two functions. It can be programmed to function as a Global Output Enable pin or a Dedicted Input pin. This pin performs one of two functions. It can be programmed to function as a Global Output Enable or a Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs one of two functions. It can be programmed to function as a Dedicated Clock Input that is brought into the Clock Distribution Network and can optionally be routed to any GLB and/or I/O cell on the device, or as an Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Input — Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input — This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. TDI/IN 0 also is used as one of the two control pins for the ISP state machine. When ispEN is high, it functions as a dedicated input pin. Input — This pin performs two functions. When ispEN is logic low, it functions as a pin to control the operation of the ISP state machine. When ispEN is high, it functions as a dedicated input pin. Output/Input — This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. Input — This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. Ground (GND) Vcc |
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