11

driving of eight 5 x 7 dot matrix

characters. The major user

accessible portions of the display

are listed below:

Flash RAM, a 128 character ASCII

decoder, a 16 character UDC

RAM, a UDC Address Register, a

Control Word Register, and the

refresh circuitry necessary to

synchronize the decoding and

Character Ram

Figure 2 shows the logic levels

needed to access the

HDSP-213X Character RAM.

During a normal access the CE =

"0" and either RD = "0" or WR =

"0". However, erroneous data may

be written into the Character RAM

if the Address lines are unstable

when CE = "0" regardless of the

logic levels of the RD or WR lines.

Address lines A

select the location in the Charac-

ter RAM. Two types of data can

be stored in each Character RAM

location: an ASCII code or a UDC

RAM address. Data bit D

to differentiate between an ASCII

character and a UDC RAM

address. D

decoder and D

UDC RAM. D

input ASCII data and D

used to input a UDC address.

Figure 2. Logic Levels to Access the Character RAM.

Character RAM

This RAM stores either ASCII character data or a UDC RAM address.

Flash RAM

This is a 1 x 8 RAM which stores Flash data.

User-Defined Character

This RAM stores the dot pattern for custom characters.

RAM (UDC RAM)

User-defined Character

This register is used to provide the address to the UDC RAM when

Address Register

the user is writing or reading a custom character.

(UDC Address Register)

Control Word Register

This register allows the user to adjust the display brightness, flash

individual characters, blink, self test or clear the display.

Display Internal Block

Diagram

Figure 1 shows the internal block

diagram of the HDSP-213X/-2179

display. The CMOS IC consists of

an 8 byte Character RAM, an 8 bit