X9260US24-27 datasheet(7/25 Pages) INTERSIL

Part #	X9260US24-27

Description	Dual Supply/Low Power/256-Tap/SPI bus

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Manufacturer	INTERSIL [Intersil Corporation]

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7

FN8170.0

February 28, 2005

DEVICE DESCRIPTION

Instructions

IDENTIFICATION BYTE ( ID AND A )

The first byte sent to the X9260 from the host,

following a CS going HIGH to LOW, is called the

Identification Byte. The most significant four bits of the

slave address are a device type identifier. The ID[3:0]

bits is the device id for the X9260; this is fixed as

0101[B] (refer to Table 3).

The AD[3:0] bits in the ID byte is the internal slave

address. The physical device address is defined by

the state of the A3 - A0 input pins. The slave address

is externally specified by the user. The X9260

compares the serial data stream with the address

input state; a successful compare of both address bits

is required for the X9260 to successfully continue the

command sequence. Only the device which slave

address matches the incoming device address sent

by the master executes the instruction. The A3 - A0

inputs can be actively driven by CMOS input signals

or tied to VCC or VSS.

INSTRUCTION BYTE ( I[3:0] )

The next byte sent to the X9260 contains the instruction

and register pointer information. The three most

significant bits are used provide the instruction opcode

(I[3:0]). The RB and RA bits point to one of the four

Data Registers of each associated XDCP. The least

significant bit points to one of two Wiper Counter

Registers or Pots.The format is shown below in Table 4.

Table 3. Identification Byte Format

Table 4. Instruction Byte Format

ID3

ID2

ID1

ID0

A3

A2

A1

A0

010

1

(MSB)

(LSB)

Device Type

Identifier

Slave Address

I3

I2

I1

I0

RB

RA

0

P0

(MSB)

(LSB)

Instruction

Data

Pot Selection

Opcode

Selection

(WCR Selection)

Register

X9260

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