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IC42S16800-8TG Datasheet(PDF) 5 Page - Integrated Circuit Solution Inc |
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IC42S16800-8TG Datasheet(HTML) 5 Page - Integrated Circuit Solution Inc |
5 / 69 page IC42S81600/IC42S81600L IC42S16800/IC42S16800L Integrated Circuit Solution Inc. 5 DR023-0E 6/11/2004 PIN FUNCTIONS Symbol Type Function (In Detail) CLK Input Pin Master Clock: Other inputs signals are referenecd to the CLK rising edge CKE Input Pin Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CS Input Pin Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Pin Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. A0-A11 Input Pin Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. The row address is specified by A0-A11. The column address is specified by A0-A9 (IC42S81600) / A0-A8 (IC42S16800) BA0,BA1 Input Pin Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. DQM, UDQM ,LDQM Input Pin Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is masked. When DQM is is high in burst read, Dout is disable at the next but one cycle. DQ0 to DQ15 I/O Pin Data Input / Output: Data bus. VDD, VSS Power Supply Pin Power Supply for the memory array and peripheral circuitry. VDDQ, VSSQ Power Supply Pin Power Supply are supplied to the output buffers only. |
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